ARM and United Microelectronics Corporation ("UMC"), a leading global semiconductor foundry, today announced the availability of a new ARM ® Artisan ® physical IP solution on 55nm to accelerate the development of ARM processor-based embedded systems and Internet of Things (IoT) applications. UMC's 55nm ultra-low-power process (55ULP) technology is emerging as an ideal solution for energy-efficient IoT applications. The new physical IP offering will enable silicon design teams to speed up and simplify the bring-up of ARM-based SoC designs for IoT and other embedded applications. For many energy-constrained applications, maximizing battery life is critical to a successful design. The Artisan physical IP platform will enhance the ULP technology from UMC with the intent to maximize power efficiency and reduce leakage. Features such as thick gate oxide support and long, multi-channel library options give SoC designers multiple tools to help optimize IoT applications. "A complete physical IP foundation platform at UMC's 55ULP process technology is vital in enabling low-power and cost-sensitive designs for emerging IoT applications," said Will Abbey, general manager, physical design group, ARM. "By delivering libraries optimized with features targeting power-efficiency, ARM and UMC are providing SoC designers with a comprehensive set of new tools." "IoT silicon designers are being asked to deliver more highly integrated solutions within more power constrained environments, and more quickly," said Shih-Chin Lin, senior director of IP development and design support division at UMC. "UMC possesses the foundry industry's most robust IoT-specific 55nm technology platform, supported by highly comprehensive IP resources to address the "always on" ultra-low power requirements of IoT products. The addition of Artisan Physical IP to our 55ULP platform immediately increases the breadth of tools we can offer to reduce complexities and time to market." The Artisan libraries will support:
- The 0.9v ultra-low voltage domain, thereby saving up to 44 percent dynamic power and 25 percent leakage power when compared to 1.2v domain operation
- Multi-channel libraries with multiple Vts to offer SoC designers leakage and performance options. Long channel libraries can be used to further reduce leakage by up to 80 percent. The Power Management Kit (PMK) enables both active and leakage power mitigation.
- Innovative thick gate oxide library will offer dramatically reduced leakage (350x lower than regular standard cells) for always ON cells. The ability of this library to interface with higher voltages (including battery voltages used in IoT devices) can also offer the advantage of negating the need for a voltage regulator.
- Next generation high-density memory compilers offer multiple integrated power modes to save state while minimizing standby leakage. Utilizing these modes will allow SoC designers to realize up to 95 percent lower leakage when compared to regular standby.
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