Micron Technology Ships First Samples Of Hybrid Memory Cube

BOISE, Idaho, Sept. 25, 2013 (GLOBE NEWSWIRE) -- Micron Technology, Inc. (Nasdaq:MU), announced today that it is shipping 2GB Hybrid Memory Cube (HMC) engineering samples. HMC represents a dramatic step forward in memory technology, and these engineering samples are the world's first HMC devices to be shared broadly with lead customers. HMC is designed for applications requiring high-bandwidth access to memory, including data packet processing, data packet buffering or storage, and computing applications such as processor accelerators. Micron expects future generations of HMC to migrate to consumer applications within three to five years.
Micron DRAM
Micron's state-of-the-art DRAM stacked atop high-performance logic.

A photo accompanying this release is available at http://www.globenewswire.com/newsroom/prs/?pkgid=21136

An industry breakthrough, HMC uses advanced through-silicon vias (TSVs)—vertical conduits that electrically connect a stack of individual chips—to combine high-performance logic with Micron's state-of-the-art DRAM. Micron's HMC features a 2GB memory cube that is composed of a stack of four 4Gb DRAM die. The solution provides an unprecedented 160 GB/s of memory bandwidth while using up to 70 percent less energy per bit than existing technologies, which dramatically lowers customers' total cost of ownership (TCO).

"The Hybrid Memory Cube is a smart fix that breaks with the industry's past approaches and opens up new possibilities," said Jim Handy, a memory analyst at Objective Analysis. "Although DRAM internal bandwidth has been increasing exponentially, along with logic's thirst for data, current options offer limited processor-to-memory bandwidth and consume significant power. HMC is an exciting alternative."

HMC's abstracted memory enables designers to devote more time to leveraging HMC's revolutionary features and performance and less time to navigating the multitude of memory parameters required to implement basic functions. It also manages error correction, resiliency, refresh, and other parameters exacerbated by memory process variation.

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