The new platform represents the eighth generation of a programmable analog front end that Semtech-Snowbush IP pioneered for handling many standards from a single silicon macro. The architecture was initially developed at 65nm and was ported to 40nm. At 28nm, the architecture has seen three generations of silicon and is shipping in production.About the SBMULTC2T28HPM28G IP Platform The SBMULTC2T28HPM28G has an analog front end (AFE) that includes the transmit (Tx) and receive (Rx) path circuitry along with auxiliary blocks for clock generation, test and biasing. The Tx driver is a highly programmable block including multiple registers to allow adjustment of TX amplitude, de-emphasis and pre-emphasis. The Rx path is also highly programmable to meet the requirements of many serial I/O applications. Advanced equalization compensation reacts to the actual channel characteristics and extracts clean data that is provided to the on-chip parallel interface. Firmware supports the calibration and adaptation in both the Rx and Tx data paths. Implemented through a digital control interface, the software provides a flexible means of adjusting performance to meet different channel characteristics. The Rx architecture includes a multi-stage continuous time linear equalizer (CTLE), passive linear equalizer (PLE) and variable gain amplifier (VGA). The receive path also includes a decision feedback equalizer (DFE) for crosstalk suppression and extended reach. All stages feature digital offset calibration and adaptive equalization to handle a range of channel conditions. The Rx architecture supports both AC and DC coupling. The RX also includes a high bandwidth data clocked CDR to achieve high jitter tolerance. The CDR relies on a digital architecture and includes a sampling phase adjustment capability. The receiver includes a non-destructive on-chip eye monitor to allow the user to “see” the eye opening at the receive slicer after the application of both transmitter and receiver equalization. This capability can be used to help adjust the transmitter and receiver equalizers and characterize link margin.
The TX architecture includes a source series terminated (SST) transmit driver with a feed forward equalizer (FFE). The FFE has per-cursor and post-cursor taps with both manual and adaptive control.The TX clock generation is based on a fractional-N LC-PLL for superior jitter performance. An advanced, digitally assisted calibration approach is supported by firmware (same as Rx). Digitally controlled calibrations include TX termination, TX PLL frequency, TX PLL amplitude, TX phase alignment and DCD. Optional digital control supports link training. The SBMULTC2T28HPM28G includes a minimal latency on-chip digital interface. Multiple parallel interface widths are supported and the digital interface is designed to inter-operate with industry available PCS and MAC (link) layer logic. Key Features of the SBMULTC2T28HPM28G IP Platform
- Aggressive low-power design approach delivers maximum power savings at high speeds
- Numerous equalization schemes are included to address a wide range of channel applications and crosstalk challenges
- Automatic calibration of key circuits to maximize performance and yield
- Programmable TX driver including amplitude and multi-tap TX equalizer
- Programmable RX equalizer including CTLE, AGC and DFE
- Silicon option without DFE for increased power savings in shorter reach applications
- Support for both AC- and DC-coupled channels
- Flexible and low-jitter clock generation based on an fractional-N LC-PLL
- Scope-on-a-chip eye monitor for on-chip performance observation
- On-chip bit error rate tester (BERT) supporting multiple PRBS and user-defined patterns
- Eight separate loopback modes
- Analog DC test pad and digital status test bus
- AC JTAG scan chains
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