The MSR820 device is a member of MoSys’ second generation Bandwidth Engine architecture and offers the highest data throughput to support high-speed 100G to 400G packet processing applications. A single command to the MSR820 replaces multiple processor calculations and up to six memory bus traversals required with traditional memory architecture. The MSR820 delivers critical performance by freeing the host to perform more complex operations, thus increasing the throughput and reducing packet cycle time while reducing board space, power and cost versus alternative solutions. Like its first generation predecessor, the Bandwidth Engine 2 family is designed to meet high reliability, carrier network equipment requirements. In addition to this baseline capability, the second generation includes MoSys' Bit Safe™ Self Test and Self Repair Technology designed to enable extensive in-field test and repair capabilities to further enhance reliability and flexibility."In order for service providers to intelligently process the exponential growth in users and data traffic in the network, increased data throughput and intelligent management and monitoring are required to maintain a positive user experience," said John Monson, VP of Marketing for MoSys. "The MSR820 device with on-board macro functions supports both of these requirements by off-loading transaction laden processes like statistics and metering from processing engines to enable higher data rates and time sensitive application functions." MoSys' first generation Bandwidth Engine ICs have been fully qualified for carrier-grade applications and are available for volume production now. The company is currently accepting sample orders for the second generation MSR820 and MSR620 devices; for information about pricing and availability, contact a local MoSys sales representative at http://www.mosys.com/contact.php. About MoSys, Inc. MoSys, Inc. (NASDAQ: MOSY) is a fabless semiconductor company enabling leading equipment manufacturers in the networking and communications systems markets to address the continual increase in Internet users, data and services. The company’s solutions deliver data path connectivity, speed and intelligence while eliminating data access bottlenecks on line cards and systems scaling from 100G to multi-terabits per second. Engineered and built for high-reliability carrier and enterprise applications, MoSys’ Bandwidth Engine® and LineSpeed™ IC product families are based on the company’s patented high-performance, high-density intelligent access and high-speed serial interface technology, and utilize the company’s highly efficient GigaChip™ Interface. MoSys is headquartered in Santa Clara, California. More information is available at http://www.mosys.com. Bandwidth Engine and MoSys are registered trademarks of MoSys, Inc. in the US and/or other countries. Bit Safe, GigaChip, LineSpeed and the MoSys logo are trademarks of MoSys, Inc. All other marks mentioned herein are the property of their respective owners.
MoSys (NASDAQ: MOSY), a leader in semiconductor solutions that enable fast, intelligent data access for network and communications systems, today announced sample availability of its Bandwidth Engine® 2 – Macro device, which, in conjunction with the highest bandwidth density and access rate, also delivers offload acceleration of management and accounting capabilities used in carrier networks. The network management functions are necessary to measure, monitor and monetize the bandwidth delivery in carrier and network operators’ infrastructure. The Bandwidth Engine 2 - Macro device delivers the billions of data access, throughput and update operations per second that are needed in order to enable real-time operations, administration and management (OAM) and real-time quality of service (QoS) to maintain high data throughput. In applications such as network routing or switching line cards with aggregate rates of 100G and beyond, the MoSys® MSR820 device provides intelligent offload for counting, statistics, metering and atomic operations. The macro functionality of the MSR820 takes advantage of its internal, highly parallel architecture and bandwidth to accelerate packet processing application performance by up to six times. As network performance scales up, the ability to perform network management functions in real time becomes more challenging, forcing systems to rely on sampling, offline or statistical behavioral analysis. The MSR820 allows packet processing engines to gather and report network performance characteristics on 100G data flows in real time, enabling operators to identify and adapt to demand and maximize asset utilization. The highly parallel array architecture is capable of up to six billion memory accesses per second and its internal processing capabilities can be saturated with only 8 SerDes lanes when utilizing the on-board macro functionality, enabling up to three billion counter operations or 1.5 billion three color meter operations per second. Coupled with the efficient, packetized, serial interface, it enables support of multiple applications within its 576 Megabit footprint. Alternative architectures often require highly complex and expensive line card designs that result in more than twice the board area and power, which is neither available nor economical.