MoSys Announces Sample Availability Of The Bandwidth Engine 2 - Macro IC With Intelligent Offload Of Statistics And Atomic Memory Operations
(NASDAQ: MOSY), a leader in semiconductor solutions that enable fast,
intelligent data access for network and communications systems, today
announced sample availability of its
MoSys (NASDAQ: MOSY), a leader in semiconductor solutions that enable fast, intelligent data access for network and communications systems, today announced sample availability of its Bandwidth Engine® 2 – Macro device, which, in conjunction with the highest bandwidth density and access rate, also delivers offload acceleration of management and accounting capabilities used in carrier networks. The network management functions are necessary to measure, monitor and monetize the bandwidth delivery in carrier and network operators’ infrastructure. The Bandwidth Engine 2 - Macro device delivers the billions of data access, throughput and update operations per second that are needed in order to enable real-time operations, administration and management (OAM) and real-time quality of service (QoS) to maintain high data throughput. In applications such as network routing or switching line cards with aggregate rates of 100G and beyond, the MoSys® MSR820 device provides intelligent offload for counting, statistics, metering and atomic operations. The macro functionality of the MSR820 takes advantage of its internal, highly parallel architecture and bandwidth to accelerate packet processing application performance by up to six times. As network performance scales up, the ability to perform network management functions in real time becomes more challenging, forcing systems to rely on sampling, offline or statistical behavioral analysis. The MSR820 allows packet processing engines to gather and report network performance characteristics on 100G data flows in real time, enabling operators to identify and adapt to demand and maximize asset utilization. The highly parallel array architecture is capable of up to six billion memory accesses per second and its internal processing capabilities can be saturated with only 8 SerDes lanes when utilizing the on-board macro functionality, enabling up to three billion counter operations or 1.5 billion three color meter operations per second. Coupled with the efficient, packetized, serial interface, it enables support of multiple applications within its 576 Megabit footprint. Alternative architectures often require highly complex and expensive line card designs that result in more than twice the board area and power, which is neither available nor economical.