Synopsys, Inc. (NASDAQ: SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced the availability of the latest release of its FineSim ™ circuit simulator. The 2012.12 release of FineSim introduces new algorithms for layout resistance and capacitance (RC) parasitic reduction and complex on-chip power network simulation, enabling up to 2X simulation speed-up and capacity for post-layout simulation of a broad range of memory designs compared to previous versions of FineSim. In addition, this release of FineSim incorporates the industry-proven HSPICE ® device modeling engine, which includes support for the FinFET BSIM-CMG 106.1 standard. The new built-in HSPICE modeling engine ensures that FineSim simulation results are consistent with HSPICE golden accuracy simulations. "SK Hynix has deployed FineSim as its primary FastSPICE circuit simulation tool for advanced-node memory timing, power and reliability verification," said Sang Il Lee, head of the Advanced Design CAE, Research and Development Division at SK Hynix. "The simulation speed and capacity improvements in the latest release of FineSim will allow us to handle the increased complexity and post-layout parasitic data of our next-generation memory designs, as well as maintain our overall memory verification productivity." Synopsys' FineSim solution provides a unique high-performance circuit simulation technology that combines FastSPICE and SPICE simulation in a single executable, enabling designers to seamlessly switch between FastSPICE and SPICE simulation with no netlist reformatting or environment changes. This unique capability provides maximum flexibility and ease-of-use for circuit designers, enabling them to take advantage of FastSPICE performance when the highest throughput is needed and switch to SPICE mode when the highest simulation accuracy is critical. FineSim's innovative multi-core/multi-machine simulation technology takes full advantage of existing compute infrastructure and can deliver superior speed and capacity scaling to shorten long simulation runs for complex memory and analog designs.