TRADE NEWS: Agilent Technologies To Showcase Bit Error Ratio Tester At DesignCon
Agilent Technologies Inc. (NYSE: A) today announced it will demonstrate
a 32-Gb/s bit error ratio tester with fast rise time and higher output
amplitude at DesignCon (Booth 201) in Santa Clara Convention Center,
Agilent Technologies Inc. (NYSE: A) today announced it will demonstrate a 32-Gb/s bit error ratio tester with fast rise time and higher output amplitude at DesignCon (Booth 201) in Santa Clara Convention Center, Jan. 29-30. A new era of data center infrastructure enabling cloud computing, big data and analytics is driving the development of new high-speed data transfer standards such as 100-Gb Ethernet and 32-Gb Fibre Channel. The higher speeds create new testing challenges for optical and electrical component designers. More stringent requirements for component characterization necessitate faster rise/fall times. Optical transceivers and transmitter optical subassemblies (TOSAs) require high drive voltages that standard pattern-generator outputs cannot supply. To address the issue, Agilent has created remotely mountable pattern-generator heads for use with its N4960A BERTs (bit error ratio testers). The new pattern-generator heads (N4951B Option H32 and Option H17) feature improved rise and fall times of 12 ps to give ASIC designers the headroom necessary for signal fidelity at the test pin. In addition, these new options integrate higher voltage output drivers into the pattern generator. This feature allows designers of optical transceivers to directly drive VCSELs, TOSAs and laser modulators for higher-data-rate applications such as 100-Gb Ethernet and OIF-CEI-28G, without the need for external driver amplifiers, associated interconnecting cables and power supplies. “Across our broad range of BERT solutions, Agilent offers choices for applications in R&D, validation and manufacturing,” said Jürgen Beck, vice president and general manager of Agilent’s Digital Photonics Test Division. “Each of our BERTs delivers accurate, repeatable results that help engineers precisely characterize performance and ensure compliance with industry standards. We have improved the rise/fall times of our 32-Gb/s N4960A serial BERT family so high-speed component designers now have the signal fidelity and headroom they need to test their next-generation devices.” As part of the N4960A BERT family, the new pattern generators are configured as remote heads connected to the BERT controller with a cable. This configuration allows the pattern generator to be located close to the device under test, minimizing the length of the signal cable, which helps minimize signal degradation.