The STAR Memory System allows hierarchical generation and verification of the test and repair IP within the SoC while maintaining the original design hierarchy. This can speed up design and verification time while allowing reuse of existing design constraints and configuration files, reducing the overall SoC design time. The combination of these new features reduces total test and repair area by up to 30 percent compared to the previous generation product, while enabling faster design closure. These capabilities can also reduce the time required for silicon bring-up and defect analysis for yield optimization, enabling the ramp to volume production to occur in weeks rather than months.The solution allows at-speed test and repair of high-performance processor cores by using a preconfigured test bus, which provides access to the memories inside the core in test mode. The system uses this bus to test memories and adds memory test and repair logic outside the IP core to avoid any impact on processor core performance. Designed for use with repairable and non-repairable memories for any foundry or process node, the STAR Memory System provides integration with Synopsys' DesignWare Embedded Memories by hardening the timing-critical test and repair logic within the memories, further improving performance, power and area as well as test quality. In combination with Synopsys' comprehensive portfolio of synthesis-based test solutions including TetraMAX ® ATPG and DFTMAX™ compression, DesignWare SerDes IP with built-in self-test and Yield Explorer ® tool for yield analysis, the STAR Memory System provides a complete test solution suite to quickly meet overall test cost and quality goals. "For 20-nanometer SoC designs, implementing robust, area-efficient memory test and repair IP is critical to managing manufacturing yield," said John Koeter, vice president of marketing for IP and systems at Synopsys. "The latest STAR Memory System release not only improves fault coverage and repair, but does so while reducing silicon area by almost a third, enabling engineering teams to get their 20-nanometer designs to market faster with lower manufacturing costs." Availability and Resources The DesignWare Star Memory System is available now.
- Learn more about the DesignWare STAR Memory System:
- Visit Synopsys booth at ITC for live demo and discussions: http://www.itctestweek.org/
- Learn more about other Synopsys test automation products: http://www.synopsys.com/Tools/Implementation/RTLSynthesis/Test/Pages/default.aspx