MoSys’ Bandwidth Engine family of ICs utilizes the GigaChip™ Interface, an open, 90% efficient, reliable transport protocol optimized for chip-to-chip communications. The device is compatible with CEI-11G and XFI SerDes, which allows a seamless interface with high performance FPGAs as well as standard libraries available from ASIC providers. A complete package of RTL and tools is available to support the Bandwidth Engine interface.MoSys' Bandwidth Engine IC has been fully qualified for carrier-grade applications and is available for volume production now. For information about Bandwidth Engine pricing and availability, contact a local MoSys sales representative at http://www.mosys.com/contact.php. About MoSys, Inc. MoSys, Inc. (NASDAQ: MOSY) is an IP-rich fabless semiconductor company that provides high performance solutions for fast, intelligent data access in network and communications systems. Engineered and built for high-reliability carrier and enterprise applications, MoSys' products are breaking bandwidth barriers(TM) in data processing to allow for faster packet access and analysis, expanded user capacity and new capabilities required by the expanding global infrastructure. MoSys' Bandwidth Engine ® family of ICs combines the company's patented 1T-SRAM(R) high-density, embedded memory and high-speed, 10 Gigabits per second serial interface with its intelligent access technology and a highly efficient GigaChip(TM) Interface transport protocol to eliminate bottlenecks in high-speed data access. MoSys is headquartered in Santa Clara, California, and more information is available at http://www.mosys.com. MoSys, 1T-SRAM and Bandwidth Engine are registered trademarks of MoSys, Inc. in the US and/or other countries. Breaking Bandwidth Barriers, GigaChip and the MoSys logo are trademarks of MoSys, Inc. All other marks mentioned herein are the property of their respective owners.
MoSys (NASDAQ: MOSY), a leader in semiconductor solutions that enable fast, intelligent data access for network and communications systems, today announced a second generation Bandwidth Engine device optimized for high-speed buffering applications. The device is based on a second generation architecture that includes higher speed interfaces and adds industry leading Intelligent Error Management capabilities. The Bandwidth Engine family of ICs is designed and built for high-reliability, carrier-grade applications. The MSR620 extends the Bandwidth Engine capabilities by incorporating cycle selectable burst functionality to support variable packet sizes with improved interface efficiency. The high access rates and effective throughput on the MSR620 buffer device are well suited to the requirements for 200GE and 400GE traffic management, packet classification, oversubscription buffering or egress buffering. Using sixteen 15 Gigabits per second (Gbps) SerDes lanes, the MSR620 interface operates at 480 Gbps, providing the host with up to 384 Gbps CRC protected, effective data throughput. This represents an unprecedented 80% overall efficiency, well beyond the capability of standard memory subsystems and alternative serial interface solutions, while occupying less board area, using fewer interface pins, and consuming less power. With finer process geometries and lower voltages, error susceptibility is inherent and a growing issue. The second generation Bandwidth Engine architecture keeps ahead of this curve by making advanced built-in self test and repair capabilities available to customers. This optional feature is another layer of protection enabling customers to deliver systems with enhanced uptime performance. “The addition of the burst functionality and higher interface rates gives the MSR620 unparalleled performance in high data rate applications while reducing board area, power and system cost," stated John Monson, Vice President of Marketing for MoSys. "Already leading the industry with Bandwidth Engine access rates, throughput and integrated intelligence, we are also excited to be at the forefront of the growing requirement for self-healing solutions. These capabilities will become more critical as geometries and voltages continue to shrink.”