Http://www.smics.com

Mentor Graphics Corp. (NASDAQ:MENT) and Semiconductor Manufacturing International Corporation ("SMIC") (NYSE:SMI) (SEHK:0981) today announced that SMIC is using the Calibre® PERC circuit reliability verification solution as part of its latest electrostatic discharge (ESD) protection design methodology. SMIC’s approach helps ensure whole chip ESD protection for its customers’ large, complex SoCs, including all I/Os, embedded IP blocks from SMIC or third-party sources, and eFuse embedded memory. SMIC adopted the Calibre PERC solution because it provides the unique ability to automatically combine schematic (netlist) and physical layout criteria and measurements to perform advanced reliability checks that until now were primarily done manually.

“New applications and use models create more difficult ESD protection challenges for designers due to increasing breakdown voltage variability, and a greater number of vulnerable circuit nodes at the interfaces between voltage domains in low power designs,” said Tianshen Tang, vice president of design service at SMIC. “We offer a multi-pronged approach that includes robust ESD protection in our IP libraries, running circuit checks for our customers using Calibre PERC with SMIC rule decks, and consulting services to assist customers with their specific ESD performance and reliability needs. We will also issue Calibre PERC design kits for our customers by mid-year so they can define and run their own checks.”

SMIC uses the Calibre PERC platform’s Logic-Driven-Layout analysis capability to ensure that all designs, including SMIC IP libraries and customer designs, conform to SMIC’s enhanced ESD design rules. Some of the key ESD protection techniques include:
  • Integrated ESD protection with a common ESD ground bus for the entire I/O ring to ensure safe discharge
  • Cross-voltage domain and analog-digital interface protection
  • Fast trigger protection devices for enhanced design margin
  • Low leakage protection circuits and high latch-up immunity
  • Local ESD protection for IP cores and eFuse memories

The Calibre PERC product not only detects violations, but provides designers with a holistic environment for debugging circuit reliability problems with an integrated view of circuit connectivity, topology, physical layout and design rules that is not available in any other tool.

If you liked this article you might like

A Sale of Citrix Would Complete Multi-Year Effort for Activist Elliott Management

Advanced Micro Devices Soars on Rumored Intel Deal

What the Pros at Honeywell, Siemens Learned About Pruning Hedges

Ranking the Activists for Proxy Season 2016

Synopsis Maintains Momentum