Built-in clock training control functionalityEssential for new DDR4-SDRAM and GDDR5-SDRAM device test, clock training functionality is built into the T5511’s hardware. This allows throughput improvements impossible when relying on software for this function. Simpler test program creation The T5511 also features a hardware CRC code generator function, necessary for cutting-edge DDR4-SDRAM and GDDR5-SDRAM device test. The dedicated hardware generates CRC codes automatically, reducing the burden on the operator and making it simpler to create test programs. Additionally, the T5511 runs Advantest’s “Future Suite” tester OS, allowing operators to utilize the extensive library of program data created for T55xx series test systems. “Lab to fab” flexibility System configurations range from 384 pins for R&D use through to a maximum of 6,144 pins for volume production. The T5511’s “lab to fab” flexible configurability allows customers to hold capital investment to a minimum, while achieving maximum test efficiency.
|Target devices:||DDR4-SDRAM, GDDR5-SDRAM|
|Parallel test capacity:||256 (x8 I/O)|
|Maximum test speed:||4GHz / 8Gbps|
|Strategic Business Unit, Global Marketing|