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In addition to financial results prepared in accordance with generally-accepted accounting principles, or GAAP, we will also present certain non-GAAP financial measures today. Cadence management believes that in addition to using GAAP results in evaluating our business, it can also be useful to measure results using certain non-GAAP financial measures. Investors and potential investors are encouraged to review the reconciliation of non-GAAP financial measures with the most direct comparable GAAP financial results which can be found in the quarterly earnings section of the Investor Relations portion of our website.A copy of today's press release dated April 25, 2012, for the quarter ended December 31, 2011 and related financial tables can also be found in the Investor Relations portion of our website. Now I'll turn the call over to Lip-Bu. Lip-Bu Tanb Good afternoon everyone and thank you for joining us. Cadence is off to a good start for 2012 for both software and hardware exceeding expectation for Q1. The quarter included two major renewal in North America and Japan. For Q1 revenue totaled $316 million. Non-GAAP operating margin was 21%, and we generated $61 million of operating cash flow. Based on Q1 results and our visibility into the rest of 2012, we are updating our outlook. Geoff will present the details in a few minutes. Let us look at the few of the highlights for Q1. I will start with silicon realization. We have significantly increased, improved our digital design flow over the last three years. In Q1, we introduced version 11.1 of our Encounter RTL-to-GDSII flow for high performance and large scale design at 20-nanometers. This new version includes in-design double-patterning support for the 20-nanometer silicon. The growing strength of our digital flow enables us to pursue additional opportunities. At the most advance nodes, for designs using advance multi-core processors and for high performance mixed signal designs.
In Q1, a major North American customer of our virtual custom and analog design flow replace the existing digital flow with the Cadence Encounter digital flow in order to deploy a fully integrated mixed signal design flow. A major European customer also renewed a commitment to our mixed signal flow in Q1.These wins for lower trend we started to see in recent quarters which is the need for integrated mix signal design and verification solution. Our market segment leading Virtuoso product lines enables us to deliver value added solutions when integrated with our Encounter and incisive platforms to meet this market requirement. In Q1 Virtuoso AMS Designer, our mixed signal simulation product won the 2012 ACE award in China in the category of best EDA product. AMS Designer is used to verify mixed signal SoCs like those used in mobile devices. DSM Technology is a key requirement for manufacturing SoCs at advance process nodes. We work closely with Samsung foundry to develop DSM flows for in-design optimization and physical sign-off for 32, 28 and 20-nanometer SoC designs. This new flows improved chip yield by addressing critical random and systematic yield issues. We are seeing an increase in interest for design solutions for 3D-IC. Cadence invested early in this space working closely with several leading customers. With TSMC we collaborated on the Test Vehicle, implying 3D-IC technologies including two silicon VS to integrate an SoC and embedded DRAM on the silicon interposer. Through our continuous investment in R&D and ecosystem development, we intend to remain well positioned to capitalize on this major shift in semiconductor and manufacturing. Next let us look at the SOC realization. Expanding our design IP business is a priority for Cadence. Martin Lund joined Cadence in March to lead our SoC realization group. Martin joined us from Broadcom where he served for 12 years, most recently as Senior Vice President and General Manager for their Network Switching Business. The addition of Martin further strengthened my integrated management team.
We continue to expand our design IP portfolio in Q1 with the introduction of a high-performing, low-power, controller PHY for the LPDDR3 mobile memory standard and 40/100 Gigabit Ethernet media access controller that enables directed deployment of SoCs for networking and high-performance computing.Read the rest of this transcript for free on seekingalpha.com