Cadence Design Systems ( CDNS) Q4 2012 Earnings Call February 1, 2012 5:00 p.m. ET Executives Alan Lindstrom – Director of IR Lip-Bu Tan – President and CEO Geoff Ribar – SVP, CFO Analysts Raj Seth – Cowan & Company Rich Valera – Needham and Company Sterling Auty - JP Morgan Jay Vleeschhouwer – Griffin Securities Krish Sankar - Bank of America Merrill Lynch Mahesh Sanganeria - RBC Capital Markets Tom Diffely - D.A. Davidson Presentation Operator
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In addition to financial results prepared in accordance with generally-accepted accounting principles, or GAAP, we will also present certain non-GAAP financial measures today. Cadence management believes that in addition to using GAAP results in evaluating our business, it can also be useful to measure results using certain non-GAAP financial measures. Investors and potential investors are encouraged to review the reconciliation of non-GAAP financial measures with the most direct comparable GAAP financial results which can be found in the quarterly earnings section of the Investor Relations portion of our website.A copy of today's press release dated February 1, 2012, for the quarter ended December 31, 2011 and related financial tables can also be found in the Investor Relations portion of our website. Now I'll turn the call over to Lip-Bu. Lip-Bu Tan Good afternoon everyone and thank you for joining us. I’m pleased to report that Cadence finished a successful 2011 with a very strong Q4. For Q4, revenue totaled $308 million. Non-GAAP operating margin was 21%, and we generated $62 million of operating cash flow. For the year 2011, revenue grew 23% to $1.15 billion. Non-GAAP operating margin doubled to 18%, and operating cash flow totaled $240 million. For 2012, we are forecasting revenue growth of approximately 8% to 11%. Geoff will present our full outlook in a few minutes. Now I will recap our successes in 2011 and then provide some of our Q4 highlights. In 2011, Cadence demonstrated the readiness of our digital custom analog and [unintelligible] solutions for 20 nanometer design. We completed seven 20 nanometer test chips with companies including ARM, Samsung, TSMC, and other foundries and customers. Many more are in progress for 2012. We established our product capabilities for designing SOC using advanced multicore processors including the first ARM Cortex A15 test chip designed for the 20 nanometer TSMC silicon. 2011 was a stellar year for the Palladium XP Verification Computing Platform and increasing numbers of customers, both semiconductor and system companies now use Palladium to develop complex SOC and for hardware, software co-design.
Growing adoption of our Encounter digital solution was highlighted in 2011 by key displacements at two major semiconductor companies and significant business wins at many other customers.In 2011 our Virtuoso 6.1 strengthened its position as the platform of choice for doing custom and analog design. Virtuoso, based on the industry standard open access database is enabling a paradigm shift from traditional connectivity-driven to a more automated constraint-driven methodology that is delivering a 2x productivity improvement. To address the challenge of integrating hardware and software for complex systems, in 2011 we launched a system development suite. The suite includes two new products, the virtual system platform and rapid prototyping platform, both of which are already in production use at several customers. In 2011 we made two important acquisitions, Altos and Azuro. The Azuro technology is now offered with the Encounter digital IC design platform and has been a critical factor in winning several design benchmarks. The products we acquired with Altos are recognized as the leading solutions for IP library characterization, helping customers produce higher quality designs at advanced technology nodes. Now let us look at a few of the highlights for Q4. Business was strong across our silicon realization product line. In particular, I want to highlight our verification, mixed signal, and system silicon package [unintelligible] businesses. Today every company doing advanced, complex SOC, especially communication devices and embedded processor design needs more verification capability. Our incisive verification platform is winning business and gaining share in advanced verification because our technology and methodology advantages, incisive, matrix-driven approach, multilanguage support, mixed signal and low power features, and tight connections with Palladium XP and verification IP and crisp performance and productivity. Our verification business in Q4 was highlighted by our competitive displacement at one major semiconductor company and significant growth of our installed base with another.
Now turning to mixed signal, in Q4 yet another company using Virtuoso for analog design adopted the Encounter digital IC design platform for their low power and mixed signal flow. This demonstrates the advantage of our end-to-end flow for low power and mixed signal design, which addresses the increasing complexity of digital content in mixed signal design as well as the need for greater energy efficiency.Read the rest of this transcript for free on seekingalpha.com