Cadence Design Systems, Inc. ( CDNS) Q3 2011 Earnings Call October 26, 2011 5:00 p.m. EDT Executives Alan Lindstrom – Director of IR Lip-Bu Tan – President and CEO Geoff Ribar – SVP, CFO Analysts Paul Thomas – Bank of America Rich Valera – Needham and Company Raj Seth – Cowen and Company [Sackett] – JPMorgan Jay Vleeschhouwer – Griffin Securities Presentation Operator
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In addition to financial results prepared in accordance with generally-accepted accounting principles, or GAAP, we will also present certain non-financial GAAP financial measures today. Cadence management believes that in addition to using GAAP results in evaluating our business, it can also be useful to measure results using certain non-GAAP financial measures. Investors and potential investors are encouraged to review the reconciliation of non-GAAP financial measures with the most direct comparable GAAP financial results which can be found in the quarterly earnings section of the Investor Relations portion of our website.A copy of today's press release dated October 26, 2011 for the quarter ended October 1, 2011 and related financial tables can also be found in the Investor Relations portion of our website. Now I'll turn the call over to Lip-Bu. Lip-Bu Tan Good afternoon, everyone. Thank you for joining. The strong design activity so far in 2011 continue to drive our business in Q3. Revenue totaled $292 million, non-GAAP operating margin was 18%, and we generated $52 million of operating cash flow. Given the risk of the world economy, we looked very closely at our prospective Q4 business. As reflected in our outlook, we expect good demand in Q4 for our products and services, driven by strong design activity. Application-driven design, modality, video and cloud are key drivers of the design activity. Also, many of our customers are targeting faster, smaller, lower power devices for the mobile and consumer markets. This is very well aligned with our industry-leading position in low power and mixed signal design. In addition to strong sales across our product lines, in Q3, we also demonstrated our product readiness for 20-nanometer, and firmly established our product capabilities for designing SoCs using advanced multi-card processors. Now, let us look at our third quarter highlights. I will start with silicon realization.
The move to 32-nanometer and 28-nanometer is gaining momentum. Cadence is engaged with an increasing number of customers, designing at this advanced nodes. I will highlight a recent success later in my remarks.We have already completed multiple test chips at 20-nanometer with our silicon partners, and we have many more planned for Q4 and Q1. We are also working on [40-nanometer] projects with select partners. Our recent announcement with ARM last week illustrates our readiness for 20-nanometer as well as highlights our capability for the design of SoCs using advanced processors like ARM Cortex A15. Our engineers work side by side with engineers from ARM and TSMC to design first test chip in the world containing ARM Cortex A15 using a complex Cadence RTL to sign off design flow, and targeting TSMC 20-nanometer process. This shows the ecosystem leaders are choosing Cadence to partner with them on their most advanced design at the most advanced processors. To address the increasing cost of mixed signal design, we continue to leverage recent productivity advances of Virtuoso 6.1 into our unified mixed signal solution. As a proof point, we recently announced that ST-Ericsson achieved a 10x productivity gain by using Cadence mixed signal solution for our complex mixed signal IC targeted to the high-volume mobile phone market. Our customers are already benefiting from the integration of the recent acquired technologies from Altos and Azuro with our digital and custom analog flows. For example, TSMC is now making scripts for library characterization for TSMC foundation IP available for download from TSMC-Online. For the first time, customers using Altos library characterization product will be able to recharacterize the TSMC libraries with the same technology used by TSMC. This provides customer greater visibility into the effects of noise, timing and power at every phase of design cycle, leading to higher-quality design. Read the rest of this transcript for free on seekingalpha.com