Hewlett-Packard ( HPQ) proved that it still has the chops to be a leader in chip design. But the company may hand off its new technology to other companies rather than seek to boost its own standing in the highly competitive chip market. On Tuesday, the Palo Alto, Calif., company announced research for a new chip architecture dubbed "field programmable nanowire interconnect," which H-P said would allow chip technology to leapfrog three generations ahead of the industry's current path. The technology, details of which will be published in a British journal later this month, provides an innovative means of boosting performance by shrinking the circuits that connect the transistors on a chip. H-P's new chip architecture is specifically geared for FPGAs, or field programmable gate arrays, a type of chip used in communications and consumer electronics products. According to H-P, the new technology could be commercially viable by 2010. Dave Berman, a spokesman for H-P Labs, says the company has not yet decided whether it will actually produce a prototype of chips based on the new design itself. (Tuesday's announcement is based on modeling and simulations, as is customary at the initial stages of development.) H-P is more likely to barter the intellectual property to other chipmakers, perhaps in exchange for the right to use other patents, than it is to use the technology itself, reckons Richard Doherty, research director at industry research firm The Envisioneering Group.
"They might use this FPGA in a forthcoming mobile product, but it would probably be made by other companies," says Doherty. Traditionally, H-P has played a pioneering role in chip development, with its PA-RISC microprocessor and its partnership with Intel ( INTC) developing the Itanium processor. In recent years, however, the company has moved away from semiconductor design, phasing out the use of PA-RISC in its own products, for instance, to focus a greater portion of its R&D efforts on software and other technologies. Nonetheless, the company still designs and manufactures semiconductors for its printers, producing the chips at its Oregon chip-fabrication facility. H-P's Berman says it's premature to talk about how the company will use its newly announced chip-architecture technology. "The technology has certainly been patented, and licensing is certainly a possibility," he says. In the past few years, H-P has created an
IP licensing division intended to derive revenue from the company's investment in R&D. While H-P has not provided any specific details on the performance boost that its new chip technology can provide, Envisioneering Group's Doherty says it would need to provide something on the order of a one-third improvement in order to gain commercial acceptance. Engineers have traditionally focused on reducing transistor size as the main path toward chip advancement -- subscribing to Moore's Law. According to Moore's Law, named after Intel co-founder Gordon Moore, the number of transistors on a chip doubles every 18 months, due to the continuing ability to shrink transistor size.
"As conventional chip electronics continue to shrink, Moore's Law is on a collision course with the laws of physics," said H-P's Labs Stan Williams, one of the authors of the paper detailing the new research. Instead of shrinking the transistors, H-P has reduced the size of the circuitry that connects the transistors. The smaller circuitry frees up more space on the chip for transistors, providing improved performance and power efficiency. "What we're saying is don't worry about shrinking the transistors any further, we've figured out how you can put more
transistors on a chip, at least on an FPGA, and then wire them all together," says H-P's Berman. Shares of H-P were off 0.8%, or 36 cents, at $43.17 in midday trading Tuesday.