Cadence Design Systems Inc (CDNS)

38.86
0.43 1.10
NASDAQ : Technology
Prev Close 38.43
Open 38.39
Day Low/High 38.33 / 38.92
52 Wk Low/High 18.13 / 26.23
Volume 1.80M
Avg Volume 2.94M
Exchange NASDAQ
Shares Outstanding 280.20M
Market Cap 10.75B
EPS 0.70
P/E Ratio 44.60
Div & Yield N.A. (N.A)

Latest News

Cadence Introduces The Conformal Smart Logic Equivalence Checker

Cadence Introduces The Conformal Smart Logic Equivalence Checker

Massively parallel architecture and adaptive proof technology improve equivalence checking runtime by an average of 4X

Cadence Appoints John Wall As Next Chief Financial Officer

Cadence Appoints John Wall As Next Chief Financial Officer

Current Chief Financial Officer Geoff Ribar to Remain with Cadence As Senior Advisor Through March 2018

New Cadence Allegro PCB DesignTrue DFM Technology Accelerates New Product Development And Introduction Process

New Cadence Allegro PCB DesignTrue DFM Technology Accelerates New Product Development And Introduction Process

Industry's first comprehensive, real-time, in-design DFM technology enables PCB designers to avoid frustrating and time-consuming design-verify-fix iterations

Cadence Tools And Flows Achieve Production-Ready Certification For TSMC's 12FFC Process

Cadence Tools And Flows Achieve Production-Ready Certification For TSMC's 12FFC Process

New technologies enable chip design for emerging mid-range mobility and high-end consumer applications

Cadence Announces Legato Memory Solution, Industry's First Integrated Memory Design And Verification Solution

Cadence Announces Legato Memory Solution, Industry's First Integrated Memory Design And Verification Solution

Delivers up to 2X runtime improvement compared to existing point tool solutions

Cadence Announces Tensilica HiFi 3z DSP Architecture For Latest Mobile And Home Entertainment Applications

Cadence Announces Tensilica HiFi 3z DSP Architecture For Latest Mobile And Home Entertainment Applications

HiFi 3z DSP provides more than 1.3X better voice and audio processing performance than its industry-leading HiFi 3 DSP predecessor

Cadence Genus Synthesis Solution Enables Toshiba To Complete A Successful ASIC Tapeout With A 2X Logic Synthesis Runtime Improvement

Cadence Genus Synthesis Solution Enables Toshiba To Complete A Successful ASIC Tapeout With A 2X Logic Synthesis Runtime Improvement

Toshiba also evaluates the Genus physical optimization flow and experiences leakage power reduction

Nagoya University And Cadence Collaborate To Port AUTOSAR-Compliant TOPPERS Automotive Kernel To Tensilica Processors And DSPs

Nagoya University And Cadence Collaborate To Port AUTOSAR-Compliant TOPPERS Automotive Kernel To Tensilica Processors And DSPs

Collaboration enables embedded software engineers to accelerate development of automotive applications on AUTOSAR OS

Cadence Custom/Analog And Full-Flow Digital And Signoff Tools Enabled For GLOBALFOUNDRIES 7LP Process Node

Reference flow available for early customer engagement

Cadence Expands Online Tool Access For ARM DesignStart Customers To Accelerate SoC Design Delivery

Customers can utilize Cadence Hosted Design Solutions to begin development of mixed-signal IoT SoCs

TheStreet Quant Rating: A- (Buy)