Synopsys Inc (SNPS)

54.37
0.25 0.46
NASDAQ : Technology
Prev Close 54.62
Open 54.49
Day Low/High 54.27 / 54.61
52 Wk Low/High 39.26 / 55.21
Volume 191.06K
Avg Volume 867.30K
Exchange NASDAQ
Shares Outstanding 151.83M
Market Cap 8.32B
EPS 1.50
P/E Ratio 36.54
Div & Yield N.A. (N.A)

Latest News

Synopsys Expands DesignWare MIPI IP Portfolio With DSI And CSI-2 Device Controllers

Synopsys Expands DesignWare MIPI IP Portfolio With DSI And CSI-2 Device Controllers

Complete MIPI Display and Camera Interface IP Solutions Deliver High Bandwidth and Low Power for Mobile, Automotive and IoT SoCs

Synopsys' IC Validator Certified By TowerJazz For Signoff Physical Verification

Synopsys' IC Validator Certified By TowerJazz For Signoff Physical Verification

Brings Enhanced Design Productivity for TowerJazz's Advanced Analog/Mixed-Signal Process Technology

Synopsys' New USB 2.0 Type-C IP Cuts Power And Area For IoT Edge Applications

Synopsys' New USB 2.0 Type-C IP Cuts Power And Area For IoT Edge Applications

DesignWare IP Reduces USB Silicon Area by Up to 50 Percent with Near 0 W Standby Power Consumption for Longer Battery Life

TetraMAX II Shortens Test Pattern Generation From Days To Hours

TetraMAX II Shortens Test Pattern Generation From Days To Hours

New ATPG Engines Reduce Test Cost, Pattern Count by 25 Percent with Order of Magnitude Faster Runtime

Synopsys TetraMAX II ATPG Certified For ISO 26262 Automotive Functional Safety

Synopsys TetraMAX II ATPG Certified For ISO 26262 Automotive Functional Safety

Independent Functional Safety Evaluation Provides Highest Level of Safety-Related Tool Confidence

Synopsys TetraMAX II Speeds Test Generation For STMicroelectronics SoC Designs

Synopsys TetraMAX II Speeds Test Generation For STMicroelectronics SoC Designs

New ATPG Engines Substantially Reduce Test Pattern Count for Lower Test Cost

Toshiba Plans Deployment Of Synopsys TetraMAX II On Upcoming SoC Design

Toshiba Plans Deployment Of Synopsys TetraMAX II On Upcoming SoC Design

New ATPG Solution Reduces Pattern Count by up to 50% and Significantly Shortens ATPG Runtime

Synopsys (SNPS) Hits New Lifetime High

Synopsys (SNPS) Hits New Lifetime High

Trade-Ideas LLC identified Synopsys (SNPS) as a new lifetime high candidate

Synopsys Releases Coverity 8.5 Static Analysis Tool

Synopsys Releases Coverity 8.5 Static Analysis Tool

Strengthens Software Integrity Offering for Web and Mobile Applications, Automotive Systems and Chinese Market

Imec And Synopsys Collaborate On Interconnect Resistivity Model To Enable Early Screening Of Interconnect Technology Options At Advanced Nodes

Imec And Synopsys Collaborate On Interconnect Resistivity Model To Enable Early Screening Of Interconnect Technology Options At Advanced Nodes

Synopsys' Process Explorer and Raphael accurately simulate parasitic resistance of alternative metals and liner-barrier materials at the 7nm node and beyond

Synopsys' New HAPS Adaptor For Juno ARM Development Platform Accelerates Software Bring-up

Synopsys' New HAPS Adaptor For Juno ARM Development Platform Accelerates Software Bring-up

Adaptor Connects HAPS® Prototyping System with Juno ARM® Versatile™ Express Board to Speed SoC Prototyping and Integration for ARMv8-A based Designs

Trade-Ideas: Synopsys (SNPS) Is Today's Strong And Under The Radar Stock

Trade-Ideas: Synopsys (SNPS) Is Today's Strong And Under The Radar Stock

Trade-Ideas LLC identified Synopsys (SNPS) as a strong and under the radar candidate

Synopsys And Lattice Semiconductor Extend Multi-Year OEM Agreement For FPGA Design Software

Synopsys And Lattice Semiconductor Extend Multi-Year OEM Agreement For FPGA Design Software

Synopsys Synplify Pro Software Delivers Superior Logic Synthesis Results for Users of Lattice Semiconductor Programmable Logic Devices

Synopsys Optimizes DesignWare IP For PCI Express 4.0 Architecture To Reduce Latency By Up To 20 Percent

Synopsys Optimizes DesignWare IP For PCI Express 4.0 Architecture To Reduce Latency By Up To 20 Percent

New Enhanced PCI Express IP Supports 16 GT/s and Latest Specification, Targeting High-Performance Applications

Synopsys Announces Release 2016.06 Of The RSoft Photonic System Design Suite

Synopsys Announces Release 2016.06 Of The RSoft Photonic System Design Suite

Latest Release Delivers New Capabilities for the Design of Manufacturable Photonic Integrated Circuits

Jim Cramer -- 'The Real Market's Healthier,' So Ignore the Bears

Jim Cramer -- 'The Real Market's Healthier,' So Ignore the Bears

There is so much buying power in so many new areas.

SMIC And Synopsys Deliver 28-nm HKMG Low-Power Reference Flow

SMIC And Synopsys Deliver 28-nm HKMG Low-Power Reference Flow

Collaboration Delivers Best-In-Class Power, Performance and Area with IC Compiler II

Synopsys' New Suite Of DDR4 IP Features Increases Capacity And Reliability Of High-Performance Cloud Computing Systems

Synopsys' New Suite Of DDR4 IP Features Increases Capacity And Reliability Of High-Performance Cloud Computing Systems

DesignWare DDR4 IP Solution Enables Servers to Solve Complex Computation Problems Faster

NXP Selects Synopsys As Primary SoC Verification Solution

NXP Selects Synopsys As Primary SoC Verification Solution

Comprehensive Synopsys Solution Enables Accelerated Verification of Next-Generation SoCs including Automotive, Secure Connectivity and Smart Connected Products

Synopsys Selected As Primary Emulation Provider For NXP Semiconductors

Synopsys Selected As Primary Emulation Provider For NXP Semiconductors

4X emulation performance enables fast software schedules for next-generation SoCs

Synopsys' Next-Generation Embedded Vision Processors Boost Performance Up To 100X

Synopsys' Next-Generation Embedded Vision Processors Boost Performance Up To 100X

DesignWare EV6x Family Integrates Scalar, Vector Processors and a Convolution Neural Network Engine for High Accuracy Vision Processing

Avnet ASIC Israel Ltd. (AAI) Standardizes On Synopsys' Design Compiler Graphical To Accelerate SoC Design Cycle

Avnet ASIC Israel Ltd. (AAI) Standardizes On Synopsys' Design Compiler Graphical To Accelerate SoC Design Cycle

RTL Congestion Analysis and Tight Correlation to Place-and-Route Shorten Design Schedules and Improve Predictability

Early Adopters Of ARM Cortex-A73 CPU And Mali-G71 GPU Successfully Tape-out Using Synopsys' IC Compiler II

Early Adopters Of ARM Cortex-A73 CPU And Mali-G71 GPU Successfully Tape-out Using Synopsys' IC Compiler II

Optimized Reference Implementation Using Galaxy Design Platform Available for New ARM Cortex-A73 Processor