EZchip Semiconductor Ltd. (EZCH)
New Product Announcement Conference Transcript
September 5, 2012 10:00 AM ET
Kenny Green - CCG Investor Relations
Eli Fruchter - Chief Executive Officer
Amir Eyal - VP, Business Development
Daniel Berenbaum - MKM Partners
Joseph Wolf - Barclays Capital
Jeff Schreiner - Feltl and Co.
Jay Srivatsa - Chardan Capital Markets
Doug Rosenberg - RBC Capital Markets
Dan Harvard - Deutsche Bank
Paul McWilliams - Next Inning Technology Research
Sundeep Bajikar - Jefferies
… (Operator Instructions)
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As a reminder, this conference is being recorded, September 5, 2012. I would now like to hand the call over to Mr. Kenny Green of CCG Investor Relations. Mr. Green, please go ahead.
Thank you, Operator, and good day to everybody. I would like to welcome all of you to this conference call in which EZchip is publically reviewing the details of its new product. On behalf of all the investors, I would like thank EZchip management for hosting this call.
I’ll note that this call will -- is simultaneously webcast together with the presentation, which is accessible from the link on EZchip Investor Relations website. The presentation is also available for download from the same link.
With us on the line today are Mr. Eli Fruchter, CEO; and Mr. Amir Eyal, VP, Business Development. Eli will open the call and will walk through the presentation. Following that we will provide time for you questions. We request that in the first round, question will be kept to two questions per person, time permitting, we will poll again for questions after the first round.
In terms of Safe Harbor, the remarks of management during the presentation and the question-and-answer session may contain projections or other forward-looking statements regarding future events or the future performance of the company or the industry. Please note that the Safe Harbor statement in today’s press release also covers the content of this conference call.
And with that, I’d like to hand the call over to EZchip’s CEO, Mr. Eli Fruchter. Eli, please go ahead.
Thank you, Kenny. Good day, everyone. And welcome to our NPS conference call. It is a big day for us as we believe we are not announcing yet another NPU generation like we have done every three years in the last 12 years. We are announcing today a new concept, a paradigm shift, the NPS, a revolutionary NPU that changes the old by which customers will select and use NPUs in the future.
Market leaders are often busy designing the next order generation and miss out on changing market trends, end up late to respond and lose their leadership. NPS is introduced by us, the leader in high-speed NPUs reading the market trends right and in time and setting above very high, yet again leaving the competition far behind.
We are announcing today the NPS, assembly of network processors for smart network. The NPS is a new breed of C-programmable NPUs for the next wave of high performance, smart carrier, data center and cloud networks.
Carrier data center and cloud networks are under constant pressure to be smarter and faster, i.e. more services that has speed. Network equipment as a result needs smarter and greater processing capability or smarter and greater NPUs.
Two types of processors are available today, NPUs and CPUs. When I’m talking about CPUs, it can relate to CPU with one core, two cores, four cores or multi-core. NPUs are optimized for fastest layer 2 and 3 processing, which use micro code and can process layer 4 to 7. CPUs and C-programmable general processor for the upper layer 4 to 7, but it reduce throughput and therefore limited in performance.
NPS breaks the barriers of traditional NPUs and CPUs by using C-programmable core to process layers 2 to 7 at extremely high-speed for a combination of unmatched performance and flexibility.
Processors in networking equipment perform two main tasks, data and control plane. Data plane processors must deal with every individual packet and maintain vast performance. Control plane processors deal with applications and management rather than packets and execute millions of lines of code. The difference in functionality imposes different architecture.
Data plane architecture require hundreds of optimized processors to deal with simultaneously with millions of packets and flows, plus Traffic Manager to deal with quality of services. Control plane processors don’t require Traffic Manager and require fewer and larger code with large memory cache to execute millions of lines of code.
Today CPUs even with improved risk cores are targeting also the data plane, however, their architecture is control plane oriented and they provide insufficient performance for the data plane.
In low-speed, the CPU can execute control and data plane processing, while high-speed require different processor type for the control and data plane. Today high-speed designs can consist of three field of processors, with NPU at layer 2, 3, a CPU with multiple core at layer 4 to 7 and a control CPU for management. NPS eliminates one field collapsing three field design into two fields with the huge performance advantage and the significant reduction in both assumption and costs.
The ideal solution is with the NPS in the data plane focus on speed and the CPU in the control plane running millions of lines of code, the combination of the two will provide the best core performance results.
The NPS is unique in many aspects with technology being the first and foremost. In our 10-year old NP family that made EZchip the leading NPU supplier, we have developed special task optimized processor for layers 2, 3, called TOPs.