Cadence Design Systems
Semiconductor Manufacturing International
said they developed a low-power digital reference flow to support SMIC's advanced 90-nanometer process technology.
The reference flow, which includes support for the Cadence encounter timing system, is now available to address the increasing needs of designers developing ICs for the computing, consumer, networking and wireless markets, the San Jose, Calif.-based company said.
''We are pleased to collaborate with SMIC and launch this reference flow based on its 90-nanometer process technology," the company added. ''Our engagement with SMIC puts in place another vital link in our customers' design chain, ensuring a manufacturing aware design chain from idea to silicon. It also highlights the growing number of foundries and design houses in China that rely on the Cadence digital IC design flow.''
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