SAN JOSE, Calif. and
July 21, 2014
/PRNewswire/ -- Cavium, Inc., (NASDAQ: CAVM), a leading provider of semiconductor products that enable intelligent processing for enterprise, data center, cloud, wired and wireless networking, and Quortus, the company transforming core network functionality into edge-based applications, today announced a partnership to embed Quortus' software Evolved Packet Core (EPC) on Cavium's OCTEON Fusion family of System-on-Chip (SoC) processors for small cell base stations. The combination of Cavium's OCTEON Fusion processors, LTE stack software and low power, low cost eNodeB designs with Quortus' highly efficient, fully featured EPC software turns small cells into extremely-portable, standalone rapidly-deployable mobile networks for site-specific uses such as public safety, emergency services and military applications. This allows the private network to operate without any connection to a remote centralized core enabling new deployment paradigms.
The OCTEON Fusion family of SoCs is the industry's most powerful small cell "base station-on-a-chip" product line, providing hardware acceleration specifically designed for LTE and 3G small cells. Cavium's field-proven small cell solutions include complete software implementations (PHY + stack) and manufacturable hardware designs.
Quortus' software EPC technology distills the functionality of a core network into an application which can be installed on SoCs, commodity hardware or in the cloud. It not only reduces the cost of network deployments, but brings a level of flexibility that allows core intelligence to be placed where it is needed most, including the network edge. It is deployment-proven in a range of settings including enterprises and remote locations, on both public and private networks.
By embedding Quortus' EPC on the OCTEON Fusion processor, the entire functionality of a mobile network can be held on the same chip; this means that a single small cell can become a highly portable mobile network. Furthermore, placing the radio and core layer on the same chip reduces the complexity of interaction between both layers, enabling the implementation of advanced functionality such as meshing, macro mobility and satellite backhaul optimization features in a more efficient way.