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Teradyne, Inc. (NYSE:TER) announces the Magnum V, the next generation memory test solution in the Nextest Magnum product line designed for massively parallel memory test in the Flash, DRAM and multi chip package (MCP) marketplace.
The Magnum V’s scalable platform extends the capabilities of the Magnum product line with higher pin count, higher device under test (DUT) parallelism, higher frequency, coverage for high-speed Flash and mobile DRAM, and lower per-pin cost for achieving a lower total cost-of-test. Magnum V leverages the platform's site-based architecture with models scaling from single site engineering up to multisite massively parallel systems for production. The architecture provides all of the test resources including digital I/O, DC/HV pins, and DUT power supplies in a single tester slot with a per-site multi-core CPU for faster test times optimized for parallel test efficiency. Magnum V software builds on four generations of Magnum's platform software with extended coverage for new DRAM, NAND and MCP device requirements.
“Magnum V is one of the most successful product introductions in our history,” said Tim Moriarty, Senior Vice President of Teradyne's Memory Test Business Unit. “We are excited to announce that we have successfully ramped our manufacturing and are currently in volume shipments of both our 10,240 and 20,480 channel models, for both production and engineering applications, at multiple customer locations worldwide.”
“The key factors in our customers’ selection of Magnum V were superior test time reduction, the ability to test both Flash and DRAM on a single platform and the 1.6 Gbps performance required for concurrent single-insertion testing of MCP devices,” noted Young Kim, Senior Director of Marketing of Teradyne Memory Test Business Unit.
Craig Foster, Senior Director of Engineering of, Teradyne's Memory Test Business Unit added, “One of our key differentiators is our production interface solutions that are integrated with the Magnum V supporting industry-standard, high-parallel handlers from multiple vendors. Our tester interface unit (TIU) and device specific application (DSA) board provide scalability for future devices and reduce the design time for new production interfaces. In addition, the higher pin density of our interface will accommodate higher parallelism and/or higher pin-count devices by simply adding tester channels and DSA’s while maintaining 100% TIU compatibility.”