- Industry's lowest additive jitter: 30 fs at 100 MHz (PCIe 3.0) and 86 fs at 12 KHz to 20 MHz (HCSL at 156.25 MHz) give designers more flexibility in timing budget allocation for the entire link.
- Excellent noise rejection: High power supply rejection ratio (PSRR) of -75 dBc at 100 MHz provides improved jitter performance and better noise immunity than competitive devices, enabling robust signal integrity.
- Flexibility, universal inputs: Two universal inputs operate at up to 400 MHz and offer compatibility with any input type, including CML, LVPECL, LVDS, SSTL, HSTL, HCSL, or single-ended clocks and crystal oscillators.
- Easy to use: Pin-mode control makes it easy for system designers to turn an individual output bank on and off.
Industry's Lowest Jitter PCIe Clock Buffers For Communications, Networking And Data Center Systems
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