DALLAS, March 13, 2014 /PRNewswire/ -- Texas Instruments (TI) (NASDAQ: TXN) today introduced a pair of 4-output and 8-output high-speed current steering logic (HCSL) clock fanout buffers that support PCI Express (PCIe) Gen-1, Gen-2, Gen-3 interface standards. The LMK00334 creates four buffered copies of an input clock, while the LMK00338 produces eight buffered copies. They deliver 70 percent lower additive jitter and significantly higher supply noise rejection than competitive devices, providing system designers with ample jitter margin over the PCIe 3.0 specification. Both devices are supported in TI's new WEBENCH® Clock Architect to help simplify clock tree design for high-speed communications, networking, and data center systems, including servers, switches and routers. For more information or to order samples and an evaluation module (EVM), visit www.ti.com/lmk00338-pr.
- Industry's lowest additive jitter: 30 fs at 100 MHz (PCIe 3.0) and 86 fs at 12 KHz to 20 MHz (HCSL at 156.25 MHz) give designers more flexibility in timing budget allocation for the entire link.
- Excellent noise rejection: High power supply rejection ratio (PSRR) of -75 dBc at 100 MHz provides improved jitter performance and better noise immunity than competitive devices, enabling robust signal integrity.
- Flexibility, universal inputs: Two universal inputs operate at up to 400 MHz and offer compatibility with any input type, including CML, LVPECL, LVDS, SSTL, HSTL, HCSL, or single-ended clocks and crystal oscillators.
- Easy to use: Pin-mode control makes it easy for system designers to turn an individual output bank on and off.
The LMK00334 and LMK00338 can be combined with the
CDCM9102 and the
CDCM6208 PCIe clock generators to create a high-performance clock tree solution. TI's clock distribution and fanout buffers give clock tree designers the flexibility, performance and advanced features they need to address a broad range of communications, networking, industrial and consumer applications.
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