SAN JOSE, Calif., Jan. 27, 2014 /PRNewswire/ -- Altera Corporation (Nasdaq: ALTR) today complemented its suite of verification and board-level design tools with the release of its JNEye link analysis tool. JNEye enables designers to quickly and easily evaluate high-speed serial link performance in Altera FPGAs and SoCs. The tool combines the speed of a statistical link simulator with the accuracy of a time-domain waveform-based simulator to form a new hybrid behavioral simulation paradigm. The JNEye tool is optimized to support Altera's Generation 10 portfolio and provides users a platform for evaluating the transceiver link performance of Altera's next-generation of FPGAs and SoCs.
"We offer a comprehensive portfolio of system-level design tools that allow our customers to quickly simulate and verify how our FPGAs and SoCs will operate in their system," said Dr. Mike Peng Li, Altera Fellow. "The JNEye link analysis tool is the latest example of these solutions. Using JNEye, designers are able to quickly understand the performance of our transceivers, at a board level, and very accurately see how our devices will interoperate with other devices in the system."
The JNEye tool delivers a hybrid modeling approach that integrates device characterization models to accurately account for process, voltage and temperature (PVT) variations. The tool simplifies the evaluation of serial-link transceivers by providing real-world simulation accuracy that is otherwise not possible using industry-standard models. JNEye supports link simulations with IBIS-AMI device models where a serial link between an Altera FPGA and other transmitters or receivers can be evaluated. With the JNEye link analysis tool, designers can quickly optimize transmit and receive equalization coefficients for target bit error ratios. The tool can also be used as a post-design support tool to assist in debug and validation.
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