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TRADE NEWS: Agilent Technologies’ Newest GoldenGate Software Release Brings Wireless Standard-Compliant Design Into RFIC Designers’ Hands

Agilent Technologies Inc. (NYSE: A) today announced the latest release of GoldenGate, its RFIC simulation, verification and analysis software.

Agilent EEsof EDA’s GoldenGate 2013.10 provides RFIC designers with easy-to-use EVM-, BER- and ACPR-type measurements and enables them to quickly analyze and diagnose problem areas in large-signal analysis. Additionally, it offers a number of new capabilities to reduce simulation time and increase design efficiency.

Wireless Standard-Compliant Design

Advanced wireless standards such as LTE Advanced (4G) and 802.11ac (WLAN) put high demands on linearity, bandwidth and noise performance, which is changing the nature of transceiver IC design. GoldenGate 2013 introduces new verification test benches that allow RFIC designers to easily validate and optimize their designs using standard-compliant waveforms and measurements such as EVM/ACLR in transmitters, or sensitivity/desensitization in receivers.

“RF system simulations using the actual standard-compliant modulated signals in order to fully capture third-order nonlinearities, AM/AM and AM/PM distortions, spectral regrowth, and memory effects are crucial to develop leading-edge RF products targeting advanced wireless standards,” said Juergen Hartung, RFIC product manager at Agilent EEsof EDA. “As a result, designers are now able to identify marginal designs early, as well as overdesigns that add costly, unnecessary die area or current consumption.”

Ability to Identify and Optimize Critical Components

While GoldenGate is known for its best-in-class RF circuit simulation performance and robustness, it also provides a host of technologies to explore, analyze and optimize RF circuits early in the design cycle. With this latest release, a new sensitivity analysis has been added that can be applied when analyzing RF circuits, even when running large-signal analyses.

Additional Capabilities

GoldenGate 2013 introduces several enhancements that cover a broad range of applications, including:
  • The fast circuit envelope (FCE) model export from GoldenGate to SystemVue, which now includes noise support that is critical for any receiver test (e.g., sensitivity/desensitization). FCE creates a model that is used in SystemVue to represent the degradation due to the RFIC in system-level simulations without facing much of a performance impact.
  • Fast yield contributor support in envelope transient and S-parameter analyses, which provides a dramatic speed-up of Monte Carlo simulations for process and mismatch variations. It also provides a contributor table to identify root cause devices and/or blocks.
  • Core solver improvements, such as a new oscillator algorithm, that specifically target high-Q oscillators and high-level transient accuracy control.
  • New automatic steady-state detection and auto-harmonic estimation within initial transient, which reduces simulation time and increases design efficiency.
  • A broad range of usability enhancements within the graphical user interface, results display and post-processing functionality. Examples include new band spectrum functions for envelope transient measurements or mean value, and standard deviation for each noise source within the noise contribution table.
  • Model support for UTSOI v1.14 and v2.0, and Angelov GaN, as well as model release updates for HICUM level0 1.31 and NXP’s SiMKit version 4.0 and 4.01.

GoldenGate is the most trusted simulation, verification and analysis solution available for integrated RF circuit design within the Cadence Virtuoso design flow. Its unique simulation algorithms are optimized for the demands of today’s complex RF circuit designs, enabling full characterization of complete transceivers prior to tape-out. GoldenGate is part of Agilent EEsof’s RFIC simulation, analysis and verification solution, which also includes Momentum for 3-D planar electromagnetic simulation, SystemVue and Ptolemy wireless test benches for system-level verification, and the Advanced Design System data display for advanced data analysis.

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