SAN JOSE, Calif., Sept. 30, 2013 /PRNewswire/ -- Altera Corporation (Nasdaq: ALTR) today announced it has completed the latest upgrade to its portfolio of IP cores targeting 28 nm FPGAs and SoCs. Over the past year, Altera has released more than 15 new protocol interface IP cores that target a broad range of applications and markets. In addition, the IP cores in Altera's expanded IP portfolio have been upgraded to deliver 15 percent timing margin for faster timing closure, which allow customers to quickly integrate multiple IP cores into their designs and get to market faster.
Altera offers a comprehensive portfolio of internally developed IP cores and strategic partner IP cores that support the company's FPGA and SoC product lines. The portfolio of IP cores contains popular external memory protocols, protocol interface IP, and video and image processing IP. Some of the most recent protocol interface cores released include:
- 50G/100G/150G/200G Interlaken, targeting wireline applications
- Serial RapidIO® Gen 2 up to 6.25 Gbps per lane, targeting wireless applications
- 10/100/1000 Mbps 1588 Ethernet MAC cores, enabling precise time synchronization on Ethernet networks
- SerialLite III Streaming, enabling high bandwidth, low latency point-to-point serial data transfers across various transmission media
For a complete list of Altera's newest IP cores visit http://www.altera.com/products/ip/news/ip-whats-new.html"We continue to invest in high-performance IP cores that meet our customers' system requirements," said Alex Grbic, director of software, DSP and IP marketing at Altera. "By offering a wide variety of IP cores that are easy to integrate into designs, we provide our customers with instant support of standard technologies so they can spend valuable engineering resources on parts of the design that make their products successful." Heitec AG, an engineering and design services firm, recently completed a customer's project using Arria V GZ and Stratix V GX FPGAs for the development of a high-resolution image processing application which requires the use of multiple Altera IP cores. Stefan Purr, Project Manager Electronic System Design at Heitec AG commented, "We were on a tight deadline with our latest project that required the use of multiple FPGAs and IP cores in the design, including DDR3, PCI Express, SerialLite III Streaming, and DisplayPort. The IP solutions offered by Altera saved us a month of FPGA design and integration time, which resulted in a significant development savings for the FPGA portion of the design. In addition to the time and cost savings, the Altera IPs allowed us to concentrate on our own user-specific design blocks to provide the additional differentiation we needed to win the design."