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Mentor Graphics Tools Included In TSMC’s Reference Flow For 16nm FinFET Process Technology

Mentor Graphics Corp. (NASDAQ: MENT) today announced that it has completed enhancements to its digital tool set for TSMC’s 16nm FinFET manufacturing processes. TSMC’s 16nm Reference Flow includes new capabilities for 16nm designs in the Olympus-SoC™ place and route system, and the Calibre® physical verification and design for manufacturing (DFM) platform. TSMC and Mentor completed V0.5 Design Rule Manual (DRM) and SPICE 16nm FinFET certification and will continue the certification toward V1.0.

“We’ve worked closely with Mentor Graphics to define new capabilities needed in the IC implementation flow to realize the benefits of 16nm FinFET technology,” said Suk Lee, senior director, Design Infrastructure Marketing Division at TSMC. “The new features build on the stable design-enabling environment that Mentor has delivered at prior nodes, which includes support for multi-patterning, low-power design, lithography checking, and design for test.”

The Mentor® Olympus-SoC place and route system has been enhanced to meet the TSMC 16nm design enablement and certification requirements. Innovative methodologies to support FinFET design include pattern density-aware floor planning for early metal fill density checks, MiM capacitor insertion for IR drop improvement, and support for high-resistance layer routing/optimization enabling better quality of results. In addition, the Calibre InRoute™ product allows Olympus-SoC customers to natively invoke Calibre DRC/DFM/DP signoff engines during design for more efficient and faster manufacturing closure.

16nm technology, and FinFET transistors in particular, create the need for more accurate device and interconnect parasitic extraction. To ensure the success of customer designs at 16nm, TSMC collaborated with Mentor on the Calibre xACT™ product enhancement via tool certification to provide high-accuracy, high-performance parasitic extraction.

The Calibre YieldEnhancer product provides new capabilities in its SmartFill facility to simplify fill rules for FinFETs, and to support a fill ECO flow, which makes it faster and easier to close a design while meeting advanced fill signoff requirements.

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