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Semtech Corporation (Nasdaq: SMTC), a leading supplier of analog and mixed-signal semiconductors, today announced that its Snowbush IP group will ship a new
Silicon Intellectual Property (SiIP) platform supporting Common Electrical Interface (CEI) standards up to 28 Gigabits per second (Gbps) for deployment in high data-rate chip-to-chip and chip-to-module applications.
The SBMULTC2T28HPM28G SiIP PHY is targeted for the new generation of chips supporting emerging Exascale computing, Terabit networking, and Petabyte storage markets. Each of these markets requires a PHY developed in a CMOS-based process to support the large digital gate counts necessary in today’s SOCs. The PHY is capable of being deployed in a multi-lane macro to support the highest I/O bandwidth possible with the lowest power per bit transferred.
“We are working with Semtech-Snowbush IP, using our extensive high speed experience, to provide a high-quality solution with fully characterized operation of the 28G PHY platform on the TSMC 28nm HPM process node,” said Naveed Sherwani, CEO of ASIC design firm Open Silicon. “This ultra-low power and high-performance SerDes combined with our implementation experience will allow us to enable our ASIC customers to bring unique and differentiated solutions to market.”
“Semtech-Snowbush IP has developed mixed-signal IP for more than ten years and our IP is in products shipping in millions of units per year,” said Roger Levinson, Vice President and General Manager of the Strategy and Systems Innovation Group at Semtech. “This new generation of IP targets the chip-to-chip and chip-to-module SOC/ASIC networking market requiring 25Gbps speeds to maximize I/O bandwidth. We are leveraging our years of experience developing platform-based SerDes/PHYs to provide performance and flexibility, while continuing to focus on efficient delivery and superb customer support.”
The SBMULTC2T28HPM28G SiIP PHY can be programmed to support multiple standards each with specific electrical performance characteristics. The area, power and latency have been optimized to minimize the impact when used in an SOC, ASIC or ASSP. A post-silicon tuning capability allows customers to adapt the performance of the PHY to different operating environments.