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Altera Demonstrates Interlaken Connectivity With Cavium OCTEON® Multicore Processors

SAN JOSE, Calif., July 30, 2013 /PRNewswire/ --  Altera Corporation (NASDAQ: ALTR) today announced the interoperability of its Interlaken intellectual property (IP) core on Stratix® V FPGAs with Cavium's OCTEON multicore processors. This accomplishment simplifies an OEM's device decision-making process by ensuring chip-to-chip connectivity upfront.

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"Altera's flexible Interlaken IP enabled us to quickly show interoperability between our products," said John Bromhead, director, Solutions and Services at Cavium. "This solution gives our customers the added assurance that when they develop with Altera FPGAs and Cavium's OCTEON processors, the devices will work seamlessly together. The ease of interoperability also helps customers meet tight time-to-market windows."

The Altera® Interlaken IP core provides high throughput and performance when workloads are at their peak. Features include:

  • More than 20 parameters and settings  provide the needed flexibility for system performance tuning, scalability and interoperability
  • Data rate and lane support up to 12.5G and x24 lanes
  • Standard and customized Interlaken IP cores offered
  • Fully integrated IP deliverable, includes MAC, PCS, and PMA layers
  • Interlaken Protocol Definition v1.2 compliant

"The flexibility of our Interlaken IP core makes Altera FPGAs instantly usable with the variety of SoC, ASSP and ASIC device interfaces in the market," said Alex Grbic, director of product marketing at Altera. "Demonstrating interoperability with Cavium OCTEON devices shows both the high quality of our Interlaken IP and our commitment to proving out solutions."

The Altera Interlaken IP core is ideal for multi-terabit routers and switches for access, carrier Ethernet and data center applications that demand IP configurability to optimize for various traffic profiles, and scalability for next-generation platforms. The Interlaken IP includes Altera's technology-leading transceivers (PMA), PCS, and MAC layers. The PCS layer is hardened within the Stratix V and Arria® V FPGAs, thereby saving customers 30 to 50 percent on FPGA logic resources. In addition to resource savings, the Interlaken IP has been through extensive simulation verification and has been proven to work on internal and customer platforms.

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