Mentor Graphics Corporation
(NASDAQ:MENT) today announced that Realtek Semiconductor Corp. is now using the Calibre® PERC™ product as its production sign-off tool for performing sophisticated electrical circuit checks (ERC) on its designs. These checks help ensure robust protection against potential critical reliability issues, including electrostatic discharge (ESD). The
product has replaced the previous internal, SPICE-based approach to circuit checking, which was slow and required complex custom code development.
“Robust circuit verification, including checking for effective ESD protection, is extremely important for advanced designs with mixed-signal components,” said Jessy Chen, vice president and spokesman at Realtek. “Using PERC, we get better performance, accuracy and flexibility. PERC helps to focus our debug time on circuit issues that matter most.”
“The electrical design rule checks that our customers need to develop and automate are rapidly growing in complexity, especially in multi-voltage, mixed-signal environments,” said Shu-Wen Chang, director of Calibre Foundry Programs for the Mentor Graphics® Design-to-Silicon division. “We have continued to enhance Calibre PERC to meet these new requirements, providing a flexible and programmable platform for circuit verification. Specifically, Calibre PERC’s topological capabilities have been extended to include circuit-driven resistance and current density checking, giving customers like Realtek faster and more repeatable ways to verify that their design has met their reliability requirements.”
Calibre PERC Enables New Electrical Checks
The Calibre PERC product enables users to define electrical checks using both topology and geometric information, allowing them to verify specific device and interconnect structures and electrical characteristics. For example, it can identify the omission of required ESD protection devices on a schematic or netlist, and it can look for errant signal paths and other soft connection errors. These include well connection errors, floating devices, nets, pins, incorrect voltage supply connections, excessive series pass gates, problem-level shifter designs, antenna checks, floating wells, minimum “hot” NWELL width, and many others.