MOUNTAIN VIEW, Calif., June 25, 2013 /PRNewswire/ -- Highlights:
- Industry's first M-PCIe® IP interoperability demonstration, developed in conjunction with Intel, unveiled at PCI-SIG® Developers Conference 2013 taking place June 25 and 26, 2013 in Santa Clara, CA
- DesignWare® IP for M-PCIe, which includes the High-Speed Gear3 MIPI® M-PHY®, gives mobile device designers a low-power IP solution that reduces their time-to-market and integration risk
- Early support for M-PCIe extends Synopsys' technology leadership in PCI Express® and MIPI IP and accelerates designers' adoption of the new M-PCIe ECN
Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced the industry's first M-PCIe interoperability demonstration. The demonstration will be shown at the PCI-SIG Developers Conference 2013 and shows the successful interoperability between M-PCIe interfaces from Synopsys and Intel using M-PCIe-based switch and endpoint devices. M-PCIe is an engineering change notice (ECN) to the PCI Express (PCIe®) specification and enables designers to leverage their existing knowledge and software investments in PCI Express to reduce the power consumption of their systems-on-chips (SoCs) for low-power applications. Synopsys' M-PCIe solution, which includes silicon-proven DesignWare MIPI M-PHY technology and M-PCIe Controller IP, provides early support for the recently announced M-PCIe specification, enabling designers to accelerate development of their M-PCIe-based designs to hit critical market windows.
"Demonstrating M-PCIe interoperability with Synopsys is a significant milestone in accelerating the development of next-generation low-power mobile platforms," said Bob Gregory, ecosystem development manager, Intel Mobile and Communications Group. "The availability of robust IP, like Synopsys' M-PCIe IP solution, is an important step in integrating M-PCIe into the next generation of low power mobile devices. The IP provides designers with a proven platform for implementing the PCI Express protocol over the MIPI M-PHY."
The M-PCIe ECN to the PCI Express specification supports the low-power MIPI M-PHY by modifying the definition of the PCIe controller's physical layer. Synopsys has implemented this enhancement to its highly successful PCI Express controller IP, which has been used in over 750 designs, to work with its silicon-proven M-PHY and provide designers with a low-risk M-PCIe solution. Synopsys' implementation of the M-PCIe ECN includes the power saving features of the PCIe specification and adds support for asymmetric link widths and improved latency. The asymmetric links defined in the M-PCIe specification allow designers to provision different bandwidths in upstream and downstream directions for increased design flexibility and effective power allocation. The M-PCIe ECN also takes advantage of the M-PHY's specification for improved entry and exit latencies when going into and out of low-power modes, saving critical power for battery-powered devices.
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