MOUNTAIN VIEW, Calif.
June 12, 2013
- One design kit for optimizing all processor cores on an SoC that includes an ultra-high density memory compiler and more than 125 new standard cells and memory instances
- Delivers up to 10 percent performance improvement on host CPU cores and up to 25 percent lower power with 10 percent area reduction on GPU cores such as the Imagination Technology PowerVR Series6 IP core
- Developed in close collaboration with key partners including Imagination Technologies, CEVA and VeriSilicon
- Implement your optimized processor cores in as little as four to six weeks with Synopsys FastOpt services
Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced an extension to its DesignWare® Duet
and Logic Library IP portfolio specifically designed to enable the optimized implementation of a broad range of processor cores. The new DesignWare HPC (High Performance Core) Design Kit contains a suite of high-speed and high-density memory instances and standard cell libraries that allow system-on-chip (SoC) designers to optimize their on-chip CPU, GPU and DSP IP cores for maximum speed, smallest area or lowest power – or to achieve an optimum balance of the three for their specific application.
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"Our work with Synopsys has resulted in significant improvements in the area and energy efficiency implementations of our IP cores utilizing Synopsys' memories and standard cell libraries," said
, executive vice-president of IMGworks SoC Design at Imagination Technologies. "Our most recent project was building a PowerVR™ Series6 GPU core using cells and memories from Synopsys' HPC Design Kit. We achieved an overall reduction of 25 percent in dynamic power as well as a 10 percent area savings, with some blocks achieving a 14 percent area improvement. We also created a tuned design flow that has delivered a 30 percent improvement in implementation turnaround time."
Synopsys' broad portfolio of DesignWare IP includes silicon-proven embedded memory compilers and standard cell libraries that support a range of foundries and processes from 180 to 28 nanometers (nm) and have shipped in more than three billion chips. The DesignWare Duet Package of Embedded Memories and Logic Libraries contains all the physical IP elements needed to implement a complete SoC including standard cells, SRAM compilers, register files, ROMs, datapath libraries and Power Optimization Kits (POKs). Options for overdrive/low- voltage process, voltage and temperature (PVT) corners, multi-channel cells, and memory built-in self-test (BIST) and repair are also available. The DesignWare HPC Design Kit adds performance-, power- and area-optimized standard cells and memory instances tuned for the special speed and density requirements of advanced CPU, GPU and DSP cores.