SAN JOSE, Calif., May 21, 2013 /PRNewswire/ -- Altera Corporation (NASDAQ: ALTR) today announced its 28 nm Stratix® V GX FPGAs have achieved inclusion on the latest PCI-SIG® Integrators List for the PCI Express® (PCIe®) 3.0 specification (Gen3). At the most recent PCI-SIG workshop, Stratix V GX FPGAs successfully passed all PCI-SIG compliance and interoperability tests, completing inclusion for Stratix V on all three generations of the Integrators Lists for PCIe. With Cyclone V and Arria V devices included on the 1.1 (Gen 1) and 2.0 (Gen2) lists, Altera's entire 28 nm portfolio is now certified by the PCI-SIG as PCIe compliant at all three generations.
Also announced today is Altera's direct memory access (DMA) reference design, constructed for Stratix V customers needing to seamlessly and quickly design PCIe Gen3 solutions. Stratix V GX FPGAs feature a hardened protocol stack for PCIe Gen3 applications, demanding the highest in bandwidth, system integration and flexibility, at a reduced cost with lower total power consumption.
"The inclusion of the Stratix V FPGAs on the first ever PCIe Gen3 Integrators List is a significant accomplishment for our high-performance devices," said Patrick Dorsey, senior director of Product Marketing, Altera. "Customers needing the performance of Stratix V and PCIe Gen3 can now design systems with the confidence that the two will seamlessly work together. Additionally, our new DMA reference design makes it fast and easy to develop high-performance PCIe Gen3x8 hardware."The Altera DMA reference design highlights the capabilities of Stratix V designs that require PCIe Gen3x8. By demonstrating peak bandwidth of the theoretical maximum, the reference design shows that Altera's Gen3 solution can preserve almost all the bandwidth available in Gen3 systems or at Gen3 data rates. Also, by demonstrating simultaneous read/write at upwards of 11 GB/sec, the design shows how much bandwidth customers can take advantage of in a real-world implementation. Features of the DMA reference design include:
- Linux driver that works with the example design
- Peak throughput (142 cycles of 256-bit at 250MHz)
- 7.1 GB/s : back to back Tx Memory Write 256 Byte payload
- 7.0 GB/s : back to back Rx Read Completion Throughput
- Simultaneous read/write : 11.4GB/sec