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Synopsys DesignWare IP For PCI Express 3.0 Passes First PCI-SIG PCIe 3.0 Compliance Workshop

Stocks in this article: SNPS

MOUNTAIN VIEW, Calif., May 17, 2013 /PRNewswire/ --


  • Synopsys' DesignWare digital controller and PHY IP for PCI Express 3.0 passed PCI-SIG®'s three required Gold Tests and completed interoperability with more than the requisite 80 percent of the devices at the workshop
  • Complete PCI Express 3.0 solution, including PHY, controller and verification IP, reduces integration risk while minimizing time-to-market
  • PCI Express 3.0 controllers, optimized for high performance, low latency and low gate counts, support x1 to x16 lanes and ARM® AMBA® AXI4™, AXI3™, and AHB™ interconnect
  • Energy-efficient PCI Express 3.0 PHY offers high-performance analog front-end for robust signal integrity and is available in leading 28-nanometer (nm) process nodes

Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced that its DesignWare® PHY and digital controller IP for the PCI-SIG® PCI Express® 3.0 is the first complete solution from a single vendor to pass compliance testing at the first PCI-SIG compliance workshop for PCI Express 3.0. The PCI Express 3.0 specification increases the operating rate to 8 gigatransfers per second (GT/s), effectively doubling the bandwidth over PCI Express 2.0 to address the high-performance requirements of data center, storage and networking applications. To achieve compliance, the DesignWare PHY and controller IP passed PCI-SIG's three required Gold Tests: the electrical tests, the Protocol Test Card (PTC) and the PCIeCV software tests. In addition, the DesignWare PHY and controller IP demonstrated interoperability with more than 80 percent of the devices at the workshop, exceeding interoperability requirements. By providing a complete and compliant IP solution for PCI Express 3.0, Synopsys enables designers to immediately incorporate the high-performance PCI Express 3.0 interface into their system-on-chips (SoCs) with less risk and improved time-to-market, while helping to ensure product interoperability.

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