- SDK for OpenCL opens the world of massively-parallel FPGA-based accelerators to software programmers without FPGA experience. The OpenCL parallel programming model delivers the fastest path from code-to-hardware implementation. Software programmers targeting FPGAs achieve higher performance at significantly lower power compared to alternative hardware architectures. See today's press release for more information on the SDK for OpenCL and for more information on Altera's newly announced Preferred Board Partner Program for OpenCL.
- Qsys system integration tool provides expanded support for ARM®-based Cyclone® V SoCs. Now Qsys can generate industry-standard AMBA® AHB and APB bus interfaces in the FPGA fabric. Further, these interfaces comply with ARM's TrustZone® requirements, allowing customers to partition an entire SoC-FPGA-based system between a secure world for critical system resources and a non-secure world for everything else.
- DSP Builder design tool enables system developers to effectively implement high-performance fixed- and floating-point algorithms into their DSP designs. New features include additional math.h functions with enhanced precision and rounding parameterization, parameterizable FFT blocks for fixed- and floating-point FFTs, more efficient folding capability and improved resource sharing.
Altera Quartus II Software V13.0 Enables World's Fastest FPGA Designs
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