MOUNTAIN VIEW, Calif.
April 25, 2013
- Accelerate development of application-specific processors for embedded vision applications by taking advantage of Synopsys® Processor Designer ™ tool set, processor examples and pre-verified design methodologies
- Explore new processor architectures tailored to embedded vision requirements in hours instead of weeks
- Reduce system bring-up time by months with pre-validated embedded vision reference flows for Synopsys HAPS® FPGA-based prototypes
Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced the immediate availability of the Embedded Vision Development System, an integrated solution for the acceleration of the design of processors for embedded vision based on Synopsys' Processor Designer tool set and Synopsys' HAPS FPGA-based prototyping system. Application-specific instruction-set processors (ASIPs) are essential for meeting the power efficiency requirements of system-on-chips (SoCs) supporting high-performance embedded vision applications, such as advanced driver assistance systems (ADAS), augmented reality (AR), robotics, surveillance and gesture control. The new Synopsys Embedded Vision Development System enables designers to rapidly explore and tune processor architectures for the optimal combination of power and speed, and quickly implement the design on a HAPS FPGA-based prototype.
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"Embedded vision enables designers to add visual intelligence to systems, making them safer, smarter and more responsive," said
, founder of the Embedded Vision Alliance (
). "But embedded vision is processing-intensive and most applications demand extreme cost- and energy-efficiency while also requiring programmability to accommodate new algorithms and new functions over time. Custom processors like those enabled by the Synopsys Embedded Vision Development System often yield the best mix of performance, efficiency and flexibility. I applaud Synopsys for recognizing and supporting the growing importance of embedded vision."
The Embedded Vision Development System includes pre-verified design examples to help designers quickly implement an ASIP optimized to meet their specific SoC objectives for power consumption and performance. It provides a ready-to-use, modifiable base processor including a full C/C++ compiler, which supports all functions provided by the OpenCV library. The execution of the compiled code with the automatically-generated instruction-set simulator (ISS) is easy to profile, clearly identifying performance-intensive parts of the application, which can be accelerated by changes in the processor architecture, including memory access, register configuration and instruction set. Unlike configurable processors that rely on a fixed pipeline and register structure, this methodology removes limitations from achieving the most power- and performance-optimized custom architecture for their application. Using the automatically generated software tools, designers easily recompile and simulate the C/C++ program until they achieve their design goals.