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LG Adopts In-Design Physical Verification With IC Compiler And IC Validator After Multiple Successful Tapeouts

MOUNTAIN VIEW, Calif., April 15, 2013 /PRNewswire/ --

Highlights

  • Synopsys' In-Design physical verification with IC Validator and IC Compiler place-and-route solution accelerates LG Electronics' manufacturing closure by two weeks
  • Multiple successful tapeouts using In-Design physical verification demonstrate accelerated manufacturing closure for high-performance core design
  • LG Electronics has adopted Synopsys' IC Validator as part of their ARM ®-based design implementation flow

Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced that LG Electronics, Inc. has adopted  IC Validator, Synopsys' physical verification applications tool, as part of their design implementation flow for ARM ® processors. Key to LG Electronics' adoption was IC Validator's In-Design technology integration with Synopsys' IC Compiler place-and-route solution. In contrast to the older iterative approach of physical design followed by verification, the In-Design approach accelerated manufacturing compliance for LG Electronics by two weeks.

"Competitive implementation of ARM processors in our designs is critical to market leadership and drives our platform strategy," said Dr. Woo- Hyun Paik, Research Fellow of SIC R&D Lab, at LG Electronics. "We found IC Validator's In-Design approach to physical verification crucial to ensuring manufacturing compliance while honoring the performance, power and other constraints of complex, high-performance, energy-efficient processor design. In our recent tapeouts, we have successfully used key IC Validator capabilities, including timing-aware fill and automatic design rule checks (DRC) repair, enabling us to achieve manufacturing compliance ahead of schedule."

With feature geometries shrinking, the number and complexity of DRC needed to achieve manufacturing compliance has grown exponentially. This has rendered the traditional physical verification approach, which relies on modifications to design after the GDSII has been generated, disadvantageous. The traditional approach can create multiple discover-then-fix iterations and can lead to suboptimal results. Examples are metal-fill insertion and design-rule checking, which today are universally mandated manufacturability compliance steps. The traditional approach would require physical designers to stream out the timing-closed, post-fill design for signoff validation and then stream it back in to fix any errors, setting the stage for multiple iterations. The same concerns are also applicable to the traditional approach to generalized design rule checking after the design has been completed, potentially leading to late-stage surprises and ensuing expensive iterations that can significantly impact tapeout schedules.

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