MOUNTAIN VIEW, Calif.
April 9, 2013
- Fujitsu Semiconductor achieved silicon success and compliance with the latest DigRFv4 standard using Synopsys' DesignWare ® MIPI M-PHY IP
- DesignWare MIPI M-PHY's proven interoperability between DigRFv4 interface on the baseband side and Fujitsu Semiconductor's radio frequency integrated circuit (RFIC) helped accelerate delivery of customer's ASIC to market, enabling quick product ramp
- Fujitsu Semiconductor achieved aggressive low power consumption goals for their customer's ASIC design for multi-band mobile application
Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced that Fujitsu Semiconductor Limited is successfully shipping a 2G/3G/4G baseband processor using Synopsys' DesignWare
DigRF 3G PHY
IP. Fujitsu Semiconductor selected Synopsys' silicon-proven IP to mitigate project schedule risks and help ensure the long-term interoperability of their ASIC design customer's system-on-chip (SoC) with Fujitsu Semiconductor's RFIC products. Integrating DesignWare IP allowed Fujitsu Semiconductor to deliver an efficient, low-power and cost-effective solution.
"Our customer's next‐generation mobile devices required low‐power, high‐bandwidth connectivity, so we needed a reliable IP solution in the required process technology that was compliant with MIPI standard specifications," said
, manager, design department, wireless solution division at Fujitsu Semiconductor. "Integrating Synopsys' DesignWare DigRFv4 M‐PHY and DigRF 3G
helped ensure the successful silicon tapeout and production ramp of mobile SoCs targeting 2G/3G/4G speeds with high data rates and low power consumption."
Fujitsu Semiconductor's ASIC design services customer needed to launch its mobile platform quickly with a low-power 28-nanometer (nm) 2G/3G/4G baseband product supporting multimode, multi-band LTE, UMTS, and EDGE mobile handsets with full support for all global FDD and TDD bands. Since both the target 28-nm process technology and the MIPI specifications were being finalized in parallel with the integration of Synopsys' M-PHY into the ASIC, Synopsys and Fujitsu Semiconductor worked closely to maintain clear and consistent communication throughout the product development cycle to ensure a successful tapeout. The engineering teams were able to identify and address differences between the DigRFv4 and DigRF 3G standard specifications, keeping the project schedule on track.