ALISO VIEJO, Calif., April 5, 2013 /PRNewswire/ -- Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced it will host a single event upset (SEU) webinar titled "SEU Immunity: Is Your Design Really Safe?" on Wednesday, April 17 at 8 a.m. PDT. The webinar is intended for design engineers focused on safety-critical aviation, defense, industrial and medical applications.
Topics will include:
- SEU Overview – What they are and why they matter
- Comparison of Flash, Antifuse and SRAM FPGAs and the risks of malfunction due to SEUs
- Results of SEU tests on Flash, Antifuse, and SRAM FPGAs
Webinar attendees will receive information on the risks and consequences of configuration failures in Flash, Antifuse and SRAM FPGA technologies, as well as background information on the physical failure mechanisms associated with SEUs. To register for the webinar, please visit https://www1.gotomeeting.com/register/830266089.About Single Event Upsets (SEUs) SEUs are caused when sub-atomic particles such as neutrons strike the silicon substrate of an integrated circuit and cause binary code bits to flip, which can corrupt configuration cells in SRAM FPGAs and may cause catastrophic hardware malfunctions. Free neutrons are present at all levels in the atmosphere, at higher concentrations at higher altitudes, and are especially problematic at aviation altitudes. Sources of sub-atomic particles also exist in IC packaging materials. Microsemi's Antifuse and Flash-based FPGAs do not experience changes of configuration due to subatomic particles. This is in direct contrast to SRAM FPGAs, which can experience catastrophic changes of functionality due to SEUs affecting their configuration. Microsemi's Configuration-safe Devices Microsemi is a leading supplier of programmable logic solutions used extensively in aviation, defense, industrial and other safety critical applications due to their high reliability and immunity to configuration changes due to SEU occurrences. SmartFusion™2 SoC FPGAs:
- Meet industry standards including IEC 61508, DO254 and DO178B;
- Configuration SEU immunity of zero failures in time (FIT); and
- Only SoC FPGA that protects all its SoC embedded SRAM memories from SEU errors.
- Large and growing heritage of successful deployment in DAL-A and DAL-B safety critical aviation applications on Boeing and Airbus aircraft; and
- Wide variety of device densities and package sizes.
- SEU-hardened flip-flops use built-in triple modular redundancy (TMR); and
- QML Class V qualification and screening.