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Tabula Sets New Industry Benchmarks With A Suite Of 100G Programmable Solutions Based On The Company's ABAX2 P-Series Of 3PLDs

SANTA CLARA, Calif., March 26, 2013 /PRNewswire/ -- Tabula Inc., advancing programmable logic solutions for network infrastructure systems, today announced a comprehensive suite of high-performance packet processing solutions. The suite solves the most challenging problems posed by the transition from 10 to 40G and 100G: specifically, routing of high-performance buses, on-chip RAM throughput, and timing closure for the ultra-high-performance functions required by these systems.


The packet processing solutions, combined with Tabula's new ABAX2P1 3PLD (the first of the ABAX2 P-Series), deliver unique capabilities such as the processing of four 100G streams on a single chip, a search engine capable of supporting 100G packet traffic, and a 12x10G-to-100G bridge.  These breakthroughs are enabled by Tabula's industry-leading technologies in four key areas: 1) Programmable 3D architecture, 2) RTL compiler, 3) leading-edge process technology, and 4) 3PLD devices. Tabula will demonstrate its high-performance packet processing solutions during the company's first series of Spacetime Forums, beginning April 8 th.  This series of one-day technical seminars will continue through May across a dozen cities in North America, Asia, and Europe. Over 250 engineers from key telecom and network system OEMs are expected to attend. 

"With the migration from 10G to 40G and 100G, FPGA users are having a hard time delivering the kind of throughput needed by these systems," said Rich Wawrzyniak, Senior Market Analyst: ASIC & SoC, at Semico Research Corp. "With this set of programmable solutions, Tabula is demonstrating that their 3PLD can support four 100G streams on a single programmable device, something not achievable on other programmable solutions."

The high-performance packet processing reference design suite is composed of:

  • A 12x10G-to-100G bridge reference design kit, implementing an aggregation function commonly used in communications systems and using the ABAX2P1 device's unique high-performance bus-handling capabilities.
  • A 4x100G switch reference design kit, targeting data center migration from 10G to 40G and 100G, is made possible by the ABAX2P1 device's ability to process multiple 100G streams.
  • A 2 nd-generation Ternary Search Engine (TSE) reference design kit, delivering the high-performance search capabilities required for leading-edge routers and NGFW while showcasing the ABAX2P1 device's unmatched RAM capabilities.

To facilitate user design, the company also delivers a complete set of design examples and soft IP cores tailored for many of the most performance-critical functions found in high-performance packet processing equipment. Examples include a 600Gbps packet classifier, a 100Gbps 64-bit CRC generator, and a 1.3Tbps L2 packet parser.

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