- Sequential timing typically enables timing closure within just a few iterations. If a design fails to meet timing, Stylus shows the users not just where but also why, so they know what to change to fix it. Using sequential timing, Stylus reports multi-cycle feedback loops and paths from input to output that are actually limiting a circuit's frequency, rather than the single flop-to-flop paths that are often just artifacts of imbalanced pipelines and not intrinsic limitations to the performance of the design. Stylus automatically balances pipeline stages at sub-nanosecond resolution, completely eliminating the tedious FPGA design methodology of balancing pipelines manually, a methodology which frequently fails to converge reliably to a timing-correct solution.
- Stylus uses a novel routing-aware placement technology that provides accurate interconnect delays and resource consumption tracking early in the flow, thereby limiting downstream surprises from the router. This early feedback enables a shorter timing-closure loop, allowing designers to achieve high performance results faster and more easily.
- Stylus automates the co-optimization of performance and density that 3PLDs uniquely enable. It automatically selects the optimum number of folds for each clock domain independently,and where appropriate, replicates functional blocks to achieve the specified throughput. Thus, Stylus frees the user to specify just the desired latency and throughput without the need to parallelize the design manually to achieve high performance.
Tabula Releases Groundbreaking EDA Technologies In Support Of Its Suite Of High-Performance Packet Processing Solutions
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