Tabula Releases Groundbreaking EDA Technologies In Support Of Its Suite Of High-Performance Packet Processing Solutions
SANTA CLARA, Calif., March 26, 2013 /PRNewswire/ -- Tabula Inc., advancing high-performance programmable logic solutions for network infrastructure systems, today announced the availability of its Stylus compiler revision 2.6, which supports the company's newly announced ABAX2P1 3D Programmable Logic Device (3PLD) and its suite of high-performance packet processing solutions.
The Stylus compiler provides a synthesis, placement, and routing flow familiar to FPGA designers and uses industry-standard RTL inputs and design constraints. It automatically exploits the unique advantages of Tabula's 3D Spacetime architecture, unleashing the ABAX 2 3PLDs' unmatched capabilities and achieving unparalleled performance with surprising ease.
"The Stylus compiler enables designers to describe designs directly in terms of their intended latency and throughput without having to replicate logic or add lots of platform-specific implementation details just to meet performance," said Steve Teig, Tabula Founder and Chief Technical Officer. "The result is cleaner RTL that is not only simpler to verify but also easier to maintain and reuse."
More about the Stylus compilerStylus 2.6 integrates cutting-edge timing closure technologies including sequential timing, router-aware placement, and automatic co-optimization of performance and density.
- Sequential timing typically enables timing closure within just a few iterations. If a design fails to meet timing, Stylus shows the users not just where but also why, so they know what to change to fix it. Using sequential timing, Stylus reports multi-cycle feedback loops and paths from input to output that are actually limiting a circuit's frequency, rather than the single flop-to-flop paths that are often just artifacts of imbalanced pipelines and not intrinsic limitations to the performance of the design. Stylus automatically balances pipeline stages at sub-nanosecond resolution, completely eliminating the tedious FPGA design methodology of balancing pipelines manually, a methodology which frequently fails to converge reliably to a timing-correct solution.
- Stylus uses a novel routing-aware placement technology that provides accurate interconnect delays and resource consumption tracking early in the flow, thereby limiting downstream surprises from the router. This early feedback enables a shorter timing-closure loop, allowing designers to achieve high performance results faster and more easily.
- Stylus automates the co-optimization of performance and density that 3PLDs uniquely enable. It automatically selects the optimum number of folds for each clock domain independently,and where appropriate, replicates functional blocks to achieve the specified throughput. Thus, Stylus frees the user to specify just the desired latency and throughput without the need to parallelize the design manually to achieve high performance.
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