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Altera Introduces FPGA-Based HSR/PRP Reference Design Targeting Smart Grid Automation Equipment

NUREMBERG, Germany, Feb. 25, 2013 /PRNewswire/ -- Embedded World-- Altera Corporation (NASDAQ: ALTR) today expanded its FPGA-based solutions targeting smart energy systems by announcing a High-availability Seamless Redundancy (HSR) and Parallel Redundancy Protocol (PRP) reference design targeting smart grid substation automation equipment. Developed jointly with Flexibilis Oy, a provider of networking equipment and technologies for wireless and wired applications, the IEC 62439-3-compliant reference design includes Flexibilis Redundant Switch (FRS) intellectual property (IP) implemented on an Altera® low-power, low-cost Cyclone®-class FPGA or Cyclone V SoC. The reference design simplifies development and implementation of highly reliable mission-critical communications systems in smart grid substations.  

(Photo: http://photos.prnewswire.com/prnh/20130225/SF64403)

(Logo: http://photos.prnewswire.com/prnh/20101012/SF78952LOGO)

"A key trend today in developing a smarter power grid is bidirectional communication and real-time control of the equipment in the grid's transmission and distribution substations," said Jason Chiang, senior strategic marketing manager in Altera's Industrial Business Unit. "Our FPGA-based HSR/PRP reference design enables equipment manufactures to build flexibility, performance, reliability and product longevity into their systems while lowering system costs and future proofing designs."

The Flexibilis HSR/PRP IP included in the reference design is a triple-speed 10/100/1000 Mbps Ethernet Layer 2 switch that is scalable from 3 to 8 ports and is compliant with the IEC 62439-3 standard. The IP is optimized for use on an Altera low-power, low-cost Cyclone IV FPGA, Cyclone V FPGA or Cyclone V SoC, which feature an integrated dual-core ARM® Cortex™-A9 processor subsystem. Cyclone V SoCs enable customers to reduce component costs by implementing their HSR/PRP switch along with the associated software stacks running on the ARM processor subsystem in the FPGA. For timing synchronization, the HSR/PRP solution supports IEEE 1588 Precision Time Protocol (PTP) Version 2. Altera and Flexibilis are showcasing the FPGA-based HSR/PRP reference design in Altera's booth at Embedded World 2013, located in Hall 4, Booth 436.

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