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Cavium To Demonstrate Innovative Mobile Infrastructure Solutions For Next Generation Radio Access, Core Network, And Wireless Display Manufacturers At Mobile World Congress

SAN JOSE, Calif., Feb. 25, 2013 /PRNewswire/ -- Cavium, Inc. (NASDAQ: CAVM), a leading provider of highly integrated semiconductor products that enable intelligent processing for networking, communications and the digital home, today announced that Cavium and its PACE partners will demonstrate innovative mobile infrastructure solutions for next-generation Radio Access, Core Network and Wireless Display applications based upon OCTEON ®, OCTEON Fusion ®, PureVu ® and TurboDPI II software at Mobile World Congress, to be held February 25-28, 2013 in Barcelona.


Providers of next-generation networks continue to be challenged to handle the explosive increase in traffic because of the fast adoption of cloud technology and mobile broadband, as well as increased exchange of multimedia and video rich content. Higher traffic coupled with the need for intelligent application-aware and secure processing has shifted the bottleneck for L3 – L7 data and security services to CPU processing that requires an unprecedented level of 64-bit CPU GHz processing power and dedicated hardware acceleration. According to the Cisco Visual Networking Index (VNI), global mobile data traffic grew 70% in 2012 is expected to exceed 10 Exabytes per month by 2017.

Cavium's OCTEON MIPS64 ® processors are used in routers, switches, unified threat management (UTM) appliances, wireless LAN controllers and access points, storage switches, triple-play broadband gateways, intelligent network adaptors, 3G, 4G, WiMAX, and LTE wireless femto cells, base stations and gateways.

Cavium's OCTEON Fusion MIPS64 processors deliver breakthrough capacity and throughput for LTE small cell base stations, including micro, pico and enterprise femto base stations, through a high performance multi-core architecture with purpose-built Baseband DSP cores, extensive LTE hardware accelerators and digital front end in a single chip.

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