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CEVA Introduces MUST™ Multi-core System Technology, Adds Vector Floating-point Capabilities For CEVA-XC DSP Architecture Framework

MOUNTAIN VIEW, Calif., Feb. 19, 2013 /PRNewswire/ -- CEVA, Inc. (NASDAQ: CEVA), the leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores, today announced a suite of advanced  processor and multi-core technologies to further enhance the CEVA-XC DSP architecture framework for high performance wireless applications including wireless terminals, small cells, access points, metro and macro base-stations. Among the new enhancements are: comprehensive multi-core features, high-throughput vector floating-point processing and a complete set of co-processor engines offering power-efficient hardware-software partitioning. CEVA has collaborated closely with leading OEMs, wireless semiconductors and IP partners for the definition and optimization of these technologies.


J. Scott Gardner, Senior Analyst at The Linley Group, commented: "In addition to improving performance while reducing cost and power consumption in wireless baseband designs, the new enhancements to the CEVA-XC architecture offer SoC designers a comprehensive environment to develop and optimize high-speed data flow in multi-core designs. Furthermore, the use of ARM's latest interconnect and coherency protocols, together with advanced automated data traffic managers, as well as a dynamic scheduling software framework, position CEVA as the only DSP licensor today offering such extensive support for multi-core DSP-based SoCs. When combined with vectorized floating-point support and a wide range of coprocessor engines, the CEVA-XC architecture framework includes all the essential DSP platform components for a wide range of user equipment and infrastructure applications."

MUST™ - advanced multi-core system technology

CEVA's MUST™ is a cache-based multi-core system technology with advanced support for cache coherency, resource sharing and data management. Initially available for the CEVA-XC, MUST™ supports the integration of multiple CEVA-XC DSP cores in a symmetric multiprocessing or asymmetric multiprocessing system architecture, along with a broad range of technologies designed specifically for multi-core DSP processing. These technologies include:
  • Dynamic scheduling using shared pools of tasks,
  • Hardware event based scheduling defined via software,
  • Task and data driven shared resource management,
  • Advanced  memory hierarchy support with full cache coherency,
  • Advanced automated data traffic management without software intervention, and
  • Special prioritization scheme based on task-awareness.

To facilitate the development of advanced multi-core SoCs containing ARM® processors and multiple CEVA DSPs, CEVA has added extensive support to the CEVA-XC architecture framework for the ARM AXI4 interconnect protocol and AMBA 4 ACE cache coherency extensions. This dramatically simplifies the software development and debugging process for SoC designs, while also reducing the software cache management overhead, processor cycles and external memory bandwidth. The overall outcome is much tighter integration between the processors in the SoC, resulting in improvements in energy-efficiency and performance for the entire system.

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