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UMC Adopts Synopsys IC Validator For Pattern Matching-Based Lithography Hot-Spot Verification At 28 Nm

MOUNTAIN VIEW, Calif., Feb. 7, 2013 /PRNewswire/ --

Highlights:

  • UMC and Synopsys collaborate to address the challenge of design verification for manufacturability at advanced process nodes
  • UMC adopts IC Validator pattern-matching technology to accelerate physical signoff at 28 nm
  • Collaboration adds new benefits to In-Design physical verification with IC Compiler for UMC customers

Synopsys, Inc. (Nasdaq: SNPS),  a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced that United Microelectronics Corporation (UMC) has selected Synopsys' IC Validator physical verification product for lithography hot-spot checking at the 28-nm process node. UMC standardized on IC Validator pattern matching, a patented technology enabling ultra-fast detection of manufacturing-limiting layouts, which can dramatically accelerate final design signoff. As part of Synopsys' Galaxy Implementation Platform, IC Validator is an ideal add-on to Synopsys' IC Compiler solution for In-Design physical verification, enabling place-and-route engineers to accelerate time to tapeout by preventing late-stage surprises and minimizing manual fixes. IC Validator pattern matching extends the In-Design flow with automatic repair of lithography violations, further optimizing design turnaround time.

"UMC is constantly implementing the latest design support resources to help our customers streamline their path to silicon success," said S.C. Chien, vice president of Advanced Technology Development division at UMC. "IC Validator's pattern-matching technology allows our customers to quickly screen for challenging layout features, eliminating the need for detailed process simulation. Furthermore, using IC Compiler and In-Design technology, this checking is available to IC designers earlier in the design process, helping to mitigate risk throughout the design cycle."

Achieving lithographic printability at 28 nm and below can impose significant restrictions on physical design, including large numbers of complex design rule checks (DRC) and compute-intensive detailed process model checking. IC Validator simplifies this task with innovative, patented pattern-matching technology, which augments traditional DRC with intuitive 2D multi-shape pattern-based analysis. Pattern matching enables foundry-quality accuracy and ultra-fast performance, helping to detect lithography hot-spots significantly faster and improve time-to-tapeout.

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