- Lowest power per channel for the speed, with low noise: Using only 80 mW-per-channel at 100 MSPS and eight channels, it enables designers to increase channel count without increasing power dissipation high-density applications, while still achieving a low noise of 71 decibel full scale (dBFS) SNR.
- Reduced system cost and complexity: TI's highly integrated digital processing block integrates commonly used digital functions, such as a low-frequency noise suppression mode, digital filtering options and programmable mapping of low-voltage differential signaling (LVDS) output pins. This lowers FPGA cost and simplifies LVDS output routing, reducing the number of printed circuit board (PCB) layers and bill of materials cost.
- Reduced interface lines: Outputs data over one or two wires of LVDS pins per channel, reducing the number of interface lines. This creates a two-wire interface, which keeps the serial data rate low to further reduce FPGA cost.
TI Introduces Lowest-power Octal, 100-MSPS ADC For Medical, Industrial Imaging Applications
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