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Synopsys Announces Energy-Efficient 28-nm PCI Express 3.0 PHY With Support For 10GBASE-KR

MOUNTAIN VIEW, Calif., Jan. 29, 2013 /PRNewswire/ --

Highlights:

  • Multi-rate PHY IP spans 1.25 Gbps to 10.3 Gbps data rates to cover a broad range of protocols
  • Multiprotocol solution supports key standards: PCI Express 3.0, 10GBASE-KR, 10GBASE-KX4, 1000BASE-KX, CEI-6G-SR, SGMII and QSGMII
  • Optimized for area and power consumption with support for IEEE's Energy-Efficient Ethernet (EEE) standard to facilitate green enterprise technologies

Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced the availability of its multiprotocol DesignWare® Enterprise 10G PHY IP to address the connectivity needs of a broad range of high-end, energy efficient networking and computing applications. Optimized for long backplane interfaces in server blade chassis, switches, routers and other high-performance computing and networking systems, the 28-nanometer (nm) Enterprise 10G PHY supports multiple interface standards, including PCI Express® (PCIe®) 3.0 and 10GBASE-KR, for a flexible interconnect solution. The new DesignWare IP also implements a multi-lane PHY architecture to support data rates from 1.25 Gbps to 10.3 Gbps per lane, with capabilities to aggregate to 40 Gbps and 100 Gbps Ethernet, giving designers a proven, scalable solution to address the growing demand for additional networking bandwidth in high-speed systems-on-chips (SoCs).

"As the fastest growing protocol in the enterprise and data center market, 10 Gigabit Ethernet is becoming a key backplane interface," said Jag Bolaria, senior analyst at The Linley Group. "Our research indicates over 25% CAGR through 2016 in the number of 10 Gigabit Ethernet ports deployed in the enterprise and data centers. The growth of 10GBASE-KR ports, combined with the rapid adoption of integrated PCI Express 3.0 in multiprocessor cores, elevates the importance of Synopsys' multiprotocol SerDes IP for designers developing ASICs that embed high-speed interfaces."

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