"Disruptive, innovative silicon devices demand equally disruptive and innovative software tools. That demand has been met by this innovative toolkit for Altera 28 nm Cyclone V and Arria V SoC devices and for upcoming Altera 20 nm SoC devices," said John Cornish, executive vice president of the System Design Division at ARM. "This technical innovation has unified CPU debugging with FPGA debugging to bolster user productivity. Altera and ARM have made this advanced tool technology with premium, productivity-boosting features widely available through Altera SoC development kits and the Altera SoC Embedded Design Suite. We believe this combination will deliver valuable benefits to our mutual customers."
The ARM DS-5 toolkit suite offers the most advanced multi-core debugger in the market for the ARM architecture. It supports debugging on systems running in asymmetric multiprocessing (AMP) and symmetric multiprocessing (SMP) system configurations. It is broadly used for board bring-up, driver development, OS porting, bare-metal and Linux application development, through JTAG and Ethernet debugging interfaces, and offers Linux and RTOS awareness.
"We are very proud of the partnership and innovation in this joint work with ARM," said Vince Hu, vice president of product and corporate marketing at Altera. "The ARM DS-5 Altera Edition toolkit gives software engineers an incredibly powerful development and debugging tool, allowing for the fastest development time for our SoC devices."
Key Features and Benefits:The ARM DS-5 Altera Edition toolkit features the following capabilities:
- Software debug view adapts to include the peripheral devices programmed by the developer into the FPGA fabric, providing a seamless view of both the hard and soft peripheral register memory map of the entire SoC.
- The DS-5 Debugger simultaneously displays debug/trace data for the Cortex-A9 processor cores and CoreSight™-compliant custom logic cores implemented in the FPGA fabric.
- Altera USB Blaster JTAG debug cable supports both the DS-5 debugger and other Altera JTAG-based tools for the Altera SoC device.
- Allows non-intrusive capture and visualization of signal events in the FPGA fabric that can be time-correlated with software events and processor instruction trace.
- Supports advanced, signal-level hardware cross-triggering between the CPU and FPGA logic domains, which enables cross-domain hardware/software co-debugging.
- Includes the DS-5 Streamline performance analyzer, which correlates software thread and event information with hardware counters from both the SoC and FPGA, enabling the identification and correction of system-level bottlenecks.