SAN JOSE, Calif.
Nov. 13, 2012
(NASDAQ: ALTR) and
, a leading provider of high-performance intellectual property (IP) cores for FPGAs, today announced the immediate availability of a hardware-proven 1,600 Mbps Reduced Latency DRAM 3 (RLDRAM® 3) memory interface solution for use in its high-end 28 nm
Stratix® V FPGAs
. The RLDRAM 3 memory interface combines auto-calibrated RLDRAM 3 UniPHY IP from Altera and a full-featured RLDRAM 3 controller core from Northwest Logic to significantly simplify interface design between RLDRAM 3 memory and the FPGA while maximizing memory throughput in high-end networking applications. This jointly-developed RLDRAM 3 memory interface solution has been hardware-validated in customer designs using
RLDRAM 3 memory.
The Altera® Stratix V family of FPGAs is optimized to support Micron Technology's next-generation RLDRAM 3 memory. Stratix V devices feature a memory architecture that delivers the FPGA industry's highest system performance with low latency and high efficiency. Stratix V FPGAs enable networking equipment manufacturers to transfer voice, video and data across the Internet quickly and efficiently.
"FPGAs provide our customers with an effective way to optimize their network products to support the growth in data volume and track the changing network infrastructure," said Robert Feurle, Micron Technology's vice president of DRAM marketing. "Integrating Altera's high-end Stratix V FPGAs with RLDRAM 3 memory provides the high level of performance needed to accommodate the rapidly evolving memory requirements of our customers."
The combination of Northwest Logic's RLDRAM 3 controller core and Altera's UniPHY IP provides a complete RLDRAM 3 solution, including high-efficiency BL=2 operation, minimal timing closure issues due to operating at a quarter clock rate, and support for a broad range of RLDRAM 3 memory configurations.