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Freescale And Continental Partner On Quad-Core 32-Bit Microcontroller For Advanced Stability Applications

Continuous developments in microelectronics are helping make advanced electronic braking systems (EBS) more reliable, responsive and affordable for mainstream vehicles. To enable the next generation of EBS and chassis control systems, Freescale Semiconductor (NYSE: FSL) and Continental have joined forces to design a high-performance, quad-core microcontroller (MCU) optimized for EBS applications.

The two automotive suppliers are collaborating on a custom MCU program called Quad-core microcontroller for Automotive Safety And Reliability ( QUASAR) designed to provide the processing intelligence for Continental’s next-generation EBS products. The first device in the family integrates four e200z4 cores based on Power Architecture ® technology, making it the industry’s first quad-core automotive MCU with two pairs of cores in redundant lockstep.

“The QUASAR device is designed to be one of the most powerful, sophisticated automotive MCUs in its class,” said Dr. Adrian Traskov, IC Development Manager at Continental’s Chassis & Safety Electronic Brake Systems business unit. “Creating a device of such complexity has required close collaboration between Continental and Freescale engineering teams on all technology fronts – silicon design, software tools, simulation and modeling, and hardware platforms. We’re working in unison to develop what we think will be a breakthrough in multicore technology for the automotive industry.”

Designed to double the performance of existing MCUs, the highly integrated device contains 4.75 MB of flash memory, 256 KB of SRAM and Continental’s fail-safe technology, which meets the requirements for ISO 26262 ASIL D and SIL3 according to IEC61508 applications. Due to the full symmetry, there is no need to partition the software into safety-relevant and safety-not relevant. Different from other available safety MCUs based on functional and checker cores, the QUASAR device provides full two-channel architecture, thus allowing recovery in the case of random hardware failure to a single channel that extends system availability.

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