SAN JOSE, Calif.
Nov. 12, 2012
/PRNewswire/ -- Altera Corporation (NASDAQ: ALTR) today announced a new
Motor Control Development Framework
that delivers unprecedented system integration, scalable performance and flexibility, while at the same time significantly reducing development time and risks for motor control system designs. The framework includes a set of customizable, single and multiaxis drive-on-a-chip reference designs and a portfolio of motor control hardware development boards, coupled with a system and software design methodology, to support the diverse requirements of next-generation drive systems. Altera will demonstrate the framework at the
SPS IPS Drives
show in Nuremberg,
, in Hall 3, Stand 405 from
November 27 to 29, 2012
The framework exploits the digital signal processing (DSP) hardware and soft embedded CPU capability in Altera® Cyclone® IV and Cyclone V FPGAs, as well as the dual ARM® Cortex™-A9 MPCore™ processors in the Hard Processor Subsystem (HPS) of Altera's Cyclone® V SoC FPGAs to provide flexible and optimal hardware/software partitioning that helps designers meet their specific end-application performance needs.
"The Altera Motor Control Development Framework brings the ideal of a high-performance, drive-on-a-chip implementation to reality by combining the flexibility and performance of Altera's low-cost silicon with productive system-level design flows for motor control applications," said
, senior manager in the Industrial business unit at Altera. "By providing an integrated motor control solution, including tools, IP, development boards and design methodology, combined with our Industrial Ethernet and functional safety offerings, designers can rapidly build differentiated drive platforms that also easily scale to meet evolving and future system requirements."
The Motor Control Development Framework maximizes designer productivity by providing a system-level development environment, allowing designers to use high-level software algorithms for system management and higher-level control functions integrated with accelerated low-latency control loops implemented in the FPGA. The framework supports a model-based design methodology in MATLAB/Simulink for the development of DSP-intensive motor control loops, such as those found in field-oriented control implementations. Optimal mapping to coprocessors in the FPGA and seamless integration with software running on integrated processors is achieved through Altera's DSP Builder and Qsys system-level design tools.