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Synopsys Introduces Memory Test And Repair Solution For Designs At 20 Nanometers And Below

The STAR Memory System allows hierarchical generation and verification of the test and repair IP within the SoC while maintaining the original design hierarchy. This can speed up design and verification time while allowing reuse of existing design constraints and configuration files, reducing the overall SoC design time. The combination of these new features reduces total test and repair area by up to 30 percent compared to the previous generation product, while enabling faster design closure. These capabilities can also reduce the time required for silicon bring-up and defect analysis for yield optimization, enabling the ramp to volume production to occur in weeks rather than months.

The solution allows at-speed test and repair of high-performance processor cores by using a preconfigured test bus, which provides access to the memories inside the core in test mode. The system uses this bus to test memories and adds memory test and repair logic outside the IP core to avoid any impact on processor core performance. Designed for use with repairable and non-repairable memories for any foundry or process node, the STAR Memory System provides integration with Synopsys' DesignWare Embedded Memories by hardening the timing-critical test and repair logic within the memories, further improving performance, power and area as well as test quality.

In combination with Synopsys' comprehensive portfolio of synthesis-based test solutions including TetraMAX ® ATPG and DFTMAX™ compression, DesignWare SerDes IP with built-in self-test and Yield Explorer ® tool for yield analysis, the STAR Memory System provides a complete test solution suite to quickly meet overall test cost and quality goals.

"For 20-nanometer SoC designs, implementing robust, area-efficient memory test and repair IP is critical to managing manufacturing yield," said John Koeter, vice president of marketing for IP and systems at Synopsys. "The latest STAR Memory System release not only improves fault coverage and repair, but does so while reducing silicon area by almost a third, enabling engineering teams to get their 20-nanometer designs to market faster with lower manufacturing costs."

Availability and Resources

The DesignWare Star Memory System is available now.

About DesignWare IP

Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes complete interface IP solutions consisting of controllers, PHY and verification IP for widely used protocols, analog IP, embedded memories, logic libraries and configurable processor cores. To support software development and hardware/software integration of the IP, Synopsys offers drivers, transaction-level models, and prototypes for many of its IP products. Synopsys' HAPS® FPGA-Based Prototyping Solution enables validation of the IP and the SoC in the system context. Synopsys' Virtualizer™ virtual prototyping tool set allows developers to start the development of software for the IP or the entire SoC significantly earlier compared to following traditional methods. With a robust IP development methodology, extensive investment in quality, IP prototyping, software development and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit: http://www.synopsys.com/designware.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS) accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, its software, IP and services help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems. Learn more at www.synopsys.com.

Editorial Contacts: Sheryl Gulizia Synopsys, Inc. 650-584-8635 sgulizia@synopsys.com

Stephen Brennan MCA, Inc.  650-968-8900, ext.114 sbrennan@mcapr.com

SOURCE Synopsys, Inc.

Copyright 2011 PR Newswire. All rights reserved. This material may not be published, broadcast, rewritten or redistributed.
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